0001 Freescale i.MX Media Video Device
0002 =================================
0003
0004 Video Media Controller node
0005 ---------------------------
0006
0007 This is the media controller node for video capture support. It is a
0008 virtual device that lists the camera serial interface nodes that the
0009 media device will control.
0010
0011 Required properties:
0012 - compatible : "fsl,imx-capture-subsystem";
0013 - ports : Should contain a list of phandles pointing to camera
0014 sensor interface ports of IPU devices
0015
0016 example:
0017
0018 capture-subsystem {
0019 compatible = "fsl,imx-capture-subsystem";
0020 ports = <&ipu1_csi0>, <&ipu1_csi1>;
0021 };
0022
0023
0024 mipi_csi2 node
0025 --------------
0026
0027 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
0028 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
0029 combined with a D-PHY core mixed into the same register block. In
0030 addition this device consists of an i.MX-specific "CSI2IPU gasket"
0031 glue logic, also controlled from the same register block. The CSI2IPU
0032 gasket demultiplexes the four virtual channel streams from the host
0033 controller's 32-bit output image bus onto four 16-bit parallel busses
0034 to the i.MX IPU CSIs.
0035
0036 Required properties:
0037 - compatible : "fsl,imx6-mipi-csi2";
0038 - reg : physical base address and length of the register set;
0039 - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
0040 (the D-PHY clock), video_27m (D-PHY PLL reference
0041 clock), and eim_podf;
0042 - clock-names : must contain "dphy", "ref", "pix";
0043 - port@* : five port nodes must exist, containing endpoints
0044 connecting to the source and sink devices according to
0045 of_graph bindings. The first port is an input port,
0046 connecting with a MIPI CSI-2 source, and ports 1
0047 through 4 are output ports connecting with parallel
0048 bus sink endpoint nodes and correspond to the four
0049 MIPI CSI-2 virtual channel outputs.
0050
0051 Optional properties:
0052 - interrupts : must contain two level-triggered interrupts,
0053 in order: 100 and 101;
