0001 Freescale Pixel Pipeline
0002 ========================
0003
0004 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
0005 that supports scaling, colorspace conversion, alpha blending, rotation, and
0006 pixel conversion via lookup table. Different versions are present on various
0007 i.MX SoCs from i.MX23 to i.MX7.
0008
0009 Required properties:
0010 - compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
0011 imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
0012 - reg: the register base and size for the device registers
0013 - interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
0014 - clock-names: should be "axi"
0015 - clocks: the PXP AXI clock
0016
0017 Example:
0018
0019 pxp@21cc000 {
0020 compatible = "fsl,imx6ull-pxp";
0021 reg = <0x021cc000 0x4000>;
0022 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0023 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0024 clock-names = "axi";
0025 clocks = <&clks IMX6UL_CLK_PXP>;
0026 };
