0001 Cadence MIPI-CSI2 TX controller
0002 ===============================
0003
0004 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
0005 4 CSI lanes in output, and up to 4 different pixel streams in input.
0006
0007 Required properties:
0008 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
0009 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
0010 - reg: base address and size of the memory mapped region
0011 - clocks: phandles to the clocks driving the controller
0012 - clock-names: must contain:
0013 * esc_clk: escape mode clock
0014 * p_clk: register bank clock
0015 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
0016 implemented in hardware, between 0 and 3
0017
0018 Optional properties
0019 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
0020 - phy-names: must contain "dphy"
0021
0022 Required subnodes:
0023 - ports: A ports node with one port child node per device input and output
0024 port, in accordance with the video interface bindings defined in
0025 Documentation/devicetree/bindings/media/video-interfaces.txt. The
0026 port nodes are numbered as follows.
0027
0028 Port Description
0029 -----------------------------
0030 0 CSI-2 output
0031 1 Stream 0 input
0032 2 Stream 1 input
0033 3 Stream 2 input
0034 4 Stream 3 input
0035
0036 The stream input port nodes are optional if they are not
0037 connected to anything at the hardware level or implemented
0038 in the design. Since there is only one endpoint per port,
0039 the endpoints are not numbered.
0040
0041 Example:
0042
0043 csi2tx: csi-bridge@0d0e1000 {
0044 compatible = "cdns,csi2tx";
0045 reg = <0x0d0e1000 0x1000>;
0046 clocks = <&byteclock>, <&byteclock>,
0047 <&coreclock>, <&coreclock>,
0048 <&coreclock>, <&coreclock>;
0049 clock-names = "p_clk", "esc_clk",
0050 "pixel_if0_clk", "pixel_if1_clk",
0051 "pixel_if2_clk", "pixel_if3_clk";
0052
0053 ports {
0054 #address-cells = <1>;
0055 #size-cells = <0>;
0056
0057 port@0 {
0058 reg = <0>;
0059
0060 csi2tx_out: endpoint {
0061 remote-endpoint = <&remote_in>;
0062 clock-lanes = <0>;
0063 data-lanes = <1 2>;
0064 };
0065 };
0066
0067 port@1 {
0068 reg = <1>;
0069
0070 csi2tx_in_stream0: endpoint {
0071 remote-endpoint = <&stream0_out>;
0072 };
0073 };
0074
0075 port@2 {
0076 reg = <2>;
0077
0078 csi2tx_in_stream1: endpoint {
0079 remote-endpoint = <&stream1_out>;
0080 };
0081 };
0082
0083 port@3 {
0084 reg = <3>;
0085
0086 csi2tx_in_stream2: endpoint {
0087 remote-endpoint = <&stream2_out>;
0088 };
0089 };
0090
0091 port@4 {
0092 reg = <4>;
0093
0094 csi2tx_in_stream3: endpoint {
0095 remote-endpoint = <&stream3_out>;
0096 };
0097 };
0098 };
0099 };
