0001 Cadence MIPI-CSI2 RX controller
0002 ===============================
0003
0004 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
0005 lanes in input, and 4 different pixel streams in output.
0006
0007 Required properties:
0008 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
0009 - reg: base address and size of the memory mapped region
0010 - clocks: phandles to the clocks driving the controller
0011 - clock-names: must contain:
0012 * sys_clk: main clock
0013 * p_clk: register bank clock
0014 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
0015 implemented in hardware, between 0 and 3
0016
0017 Optional properties:
0018 - phys: phandle to the external D-PHY, phy-names must be provided
0019 - phy-names: must contain "dphy", if the implementation uses an
0020 external D-PHY
0021
0022 Required subnodes:
0023 - ports: A ports node with one port child node per device input and output
0024 port, in accordance with the video interface bindings defined in
0025 Documentation/devicetree/bindings/media/video-interfaces.txt. The
0026 port nodes are numbered as follows:
0027
0028 Port Description
0029 -----------------------------
0030 0 CSI-2 input
0031 1 Stream 0 output
0032 2 Stream 1 output
0033 3 Stream 2 output
0034 4 Stream 3 output
0035
0036 The stream output port nodes are optional if they are not
0037 connected to anything at the hardware level or implemented
0038 in the design.Since there is only one endpoint per port,
0039 the endpoints are not numbered.
0040
0041
0042 Example:
0043
0044 csi2rx: csi-bridge@0d060000 {
0045 compatible = "cdns,csi2rx";
0046 reg = <0x0d060000 0x1000>;
0047 clocks = <&byteclock>, <&byteclock>
0048 <&coreclock>, <&coreclock>,
0049 <&coreclock>, <&coreclock>;
0050 clock-names = "sys_clk", "p_clk",
0051 "pixel_if0_clk", "pixel_if1_clk",
0052 "pixel_if2_clk", "pixel_if3_clk";
0053
0054 ports {
0055 #address-cells = <1>;
0056 #size-cells = <0>;
0057
0058 port@0 {
0059 reg = <0>;
0060
0061 csi2rx_in_sensor: endpoint {
0062 remote-endpoint = <&sensor_out_csi2rx>;
0063 clock-lanes = <0>;
0064 data-lanes = <1 2>;
0065 };
0066 };
0067
0068 port@1 {
0069 reg = <1>;
0070
0071 csi2rx_out_grabber0: endpoint {
0072 remote-endpoint = <&grabber0_in_csi2rx>;
0073 };
0074 };
0075
0076 port@2 {
0077 reg = <2>;
0078
0079 csi2rx_out_grabber1: endpoint {
0080 remote-endpoint = <&grabber1_in_csi2rx>;
0081 };
0082 };
0083
0084 port@3 {
0085 reg = <3>;
0086
0087 csi2rx_out_grabber2: endpoint {
0088 remote-endpoint = <&grabber2_in_csi2rx>;
0089 };
0090 };
0091
0092 port@4 {
0093 reg = <4>;
0094
0095 csi2rx_out_grabber3: endpoint {
0096 remote-endpoint = <&grabber3_in_csi2rx>;
0097 };
0098 };
0099 };
0100 };
