0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Amphion VPU codec IP
0009
0010 maintainers:
0011 - Ming Qian <ming.qian@nxp.com>
0012 - Shijie Qin <shijie.qin@nxp.com>
0013
0014 description: |-
0015 The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
0016 on NXP i.MX8Q SoCs.
0017
0018 properties:
0019 $nodename:
0020 pattern: "^vpu@[0-9a-f]+$"
0021
0022 compatible:
0023 items:
0024 - enum:
0025 - nxp,imx8qm-vpu
0026 - nxp,imx8qxp-vpu
0027
0028 reg:
0029 maxItems: 1
0030
0031 power-domains:
0032 maxItems: 1
0033
0034 "#address-cells":
0035 const: 1
0036
0037 "#size-cells":
0038 const: 1
0039
0040 ranges: true
0041
0042 patternProperties:
0043 "^mailbox@[0-9a-f]+$":
0044 description:
0045 Each vpu encoder or decoder correspond a MU, which used for communication
0046 between driver and firmware. Implement via mailbox on driver.
0047 $ref: ../mailbox/fsl,mu.yaml#
0048
0049
0050 "^vpu_core@[0-9a-f]+$":
0051 description:
0052 Each core correspond a decoder or encoder, need to configure them
0053 separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
0054 has one decoder and one encoder.
0055 type: object
0056
0057 properties:
0058 compatible:
0059 items:
0060 - enum:
0061 - nxp,imx8q-vpu-decoder
0062 - nxp,imx8q-vpu-encoder
0063
0064 reg:
0065 maxItems: 1
0066
0067 power-domains:
0068 maxItems: 1
0069
0070 mbox-names:
0071 items:
0072 - const: tx0
0073 - const: tx1
0074 - const: rx
0075
0076 mboxes:
0077 description:
0078 List of phandle of 2 MU channels for tx, 1 MU channel for rx.
0079 maxItems: 3
0080
0081 memory-region:
0082 description:
0083 Phandle to the reserved memory nodes to be associated with the
0084 remoteproc device. The reserved memory nodes should be carveout nodes,
0085 and should be defined as per the bindings in
0086 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
0087 items:
0088 - description: region reserved for firmware image sections.
0089 - description: region used for RPC shared memory between firmware and
0090 driver.
0091
0092 required:
0093 - compatible
0094 - reg
0095 - power-domains
0096 - mbox-names
0097 - mboxes
0098 - memory-region
0099
0100 additionalProperties: false
0101
0102 required:
0103 - compatible
0104 - reg
0105 - power-domains
0106
0107 additionalProperties: false
0108
0109 examples:
0110 # Device node example for i.MX8QM platform:
0111 - |
0112 #include <dt-bindings/firmware/imx/rsrc.h>
0113
0114 vpu: vpu@2c000000 {
0115 compatible = "nxp,imx8qm-vpu";
0116 ranges = <0x2c000000 0x2c000000 0x2000000>;
0117 reg = <0x2c000000 0x1000000>;
0118 #address-cells = <1>;
0119 #size-cells = <1>;
0120 power-domains = <&pd IMX_SC_R_VPU>;
0121
0122 mu_m0: mailbox@2d000000 {
0123 compatible = "fsl,imx6sx-mu";
0124 reg = <0x2d000000 0x20000>;
0125 interrupts = <0 472 4>;
0126 #mbox-cells = <2>;
0127 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
0128 };
0129
0130 mu1_m0: mailbox@2d020000 {
0131 compatible = "fsl,imx6sx-mu";
0132 reg = <0x2d020000 0x20000>;
0133 interrupts = <0 473 4>;
0134 #mbox-cells = <2>;
0135 power-domains = <&pd IMX_SC_R_VPU_MU_1>;
0136 };
0137
0138 mu2_m0: mailbox@2d040000 {
0139 compatible = "fsl,imx6sx-mu";
0140 reg = <0x2d040000 0x20000>;
0141 interrupts = <0 474 4>;
0142 #mbox-cells = <2>;
0143 power-domains = <&pd IMX_SC_R_VPU_MU_2>;
0144 };
0145
0146 vpu_core0: vpu_core@2d080000 {
0147 compatible = "nxp,imx8q-vpu-decoder";
0148 reg = <0x2d080000 0x10000>;
0149 power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
0150 mbox-names = "tx0", "tx1", "rx";
0151 mboxes = <&mu_m0 0 0>,
0152 <&mu_m0 0 1>,
0153 <&mu_m0 1 0>;
0154 memory-region = <&decoder_boot>, <&decoder_rpc>;
0155 };
0156
0157 vpu_core1: vpu_core@2d090000 {
0158 compatible = "nxp,imx8q-vpu-encoder";
0159 reg = <0x2d090000 0x10000>;
0160 power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
0161 mbox-names = "tx0", "tx1", "rx";
0162 mboxes = <&mu1_m0 0 0>,
0163 <&mu1_m0 0 1>,
0164 <&mu1_m0 1 0>;
0165 memory-region = <&encoder1_boot>, <&encoder1_rpc>;
0166 };
0167
0168 vpu_core2: vpu_core@2d0a0000 {
0169 reg = <0x2d0a0000 0x10000>;
0170 compatible = "nxp,imx8q-vpu-encoder";
0171 power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
0172 mbox-names = "tx0", "tx1", "rx";
0173 mboxes = <&mu2_m0 0 0>,
0174 <&mu2_m0 0 1>,
0175 <&mu2_m0 1 0>;
0176 memory-region = <&encoder2_boot>, <&encoder2_rpc>;
0177 };
0178 };
0179
0180 ...
