0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
0008
0009 maintainers:
0010 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
0011
0012 properties:
0013 compatible:
0014 const: allwinner,sun8i-a83t-mipi-csi2
0015
0016 reg:
0017 maxItems: 1
0018
0019 interrupts:
0020 maxItems: 1
0021
0022 clocks:
0023 items:
0024 - description: Bus Clock
0025 - description: Module Clock
0026 - description: MIPI-specific Clock
0027 - description: Misc CSI Clock
0028
0029 clock-names:
0030 items:
0031 - const: bus
0032 - const: mod
0033 - const: mipi
0034 - const: misc
0035
0036 resets:
0037 maxItems: 1
0038
0039 ports:
0040 $ref: /schemas/graph.yaml#/properties/ports
0041
0042 properties:
0043 port@0:
0044 $ref: /schemas/graph.yaml#/$defs/port-base
0045 description: Input port, connect to a MIPI CSI-2 sensor
0046
0047 properties:
0048 reg:
0049 const: 0
0050
0051 endpoint:
0052 $ref: video-interfaces.yaml#
0053 unevaluatedProperties: false
0054
0055 properties:
0056 data-lanes:
0057 minItems: 1
0058 maxItems: 4
0059
0060 required:
0061 - data-lanes
0062
0063 unevaluatedProperties: false
0064
0065 port@1:
0066 $ref: /schemas/graph.yaml#/properties/port
0067 description: Output port, connect to a CSI controller
0068
0069 required:
0070 - port@0
0071 - port@1
0072
0073 required:
0074 - compatible
0075 - reg
0076 - interrupts
0077 - clocks
0078 - clock-names
0079 - resets
0080 - ports
0081
0082 additionalProperties: false
0083
0084 examples:
0085 - |
0086 #include <dt-bindings/interrupt-controller/arm-gic.h>
0087 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
0088 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
0089
0090 mipi_csi2: csi@1cb1000 {
0091 compatible = "allwinner,sun8i-a83t-mipi-csi2";
0092 reg = <0x01cb1000 0x1000>;
0093 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0094 clocks = <&ccu CLK_BUS_CSI>,
0095 <&ccu CLK_CSI_SCLK>,
0096 <&ccu CLK_MIPI_CSI>,
0097 <&ccu CLK_CSI_MISC>;
0098 clock-names = "bus", "mod", "mipi", "misc";
0099 resets = <&ccu RST_BUS_CSI>;
0100
0101 ports {
0102 #address-cells = <1>;
0103 #size-cells = <0>;
0104
0105 mipi_csi2_in: port@0 {
0106 reg = <0>;
0107
0108 mipi_csi2_in_ov8865: endpoint {
0109 data-lanes = <1 2 3 4>;
0110
0111 remote-endpoint = <&ov8865_out_mipi_csi2>;
0112 };
0113 };
0114
0115 mipi_csi2_out: port@1 {
0116 reg = <1>;
0117
0118 mipi_csi2_out_csi: endpoint {
0119 remote-endpoint = <&csi_in_mipi_csi2>;
0120 };
0121 };
0122 };
0123 };
0124
0125 ...
