0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A31 CMOS Sensor Interface (CSI) Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 properties:
0014 compatible:
0015 enum:
0016 - allwinner,sun6i-a31-csi
0017 - allwinner,sun8i-a83t-csi
0018 - allwinner,sun8i-h3-csi
0019 - allwinner,sun8i-v3s-csi
0020 - allwinner,sun50i-a64-csi
0021
0022 reg:
0023 maxItems: 1
0024
0025 interrupts:
0026 maxItems: 1
0027
0028 clocks:
0029 items:
0030 - description: Bus Clock
0031 - description: Module Clock
0032 - description: DRAM Clock
0033
0034 clock-names:
0035 items:
0036 - const: bus
0037 - const: mod
0038 - const: ram
0039
0040 resets:
0041 maxItems: 1
0042
0043 port:
0044 $ref: /schemas/graph.yaml#/$defs/port-base
0045 description: Parallel input port, connect to a parallel sensor
0046
0047 properties:
0048 endpoint:
0049 $ref: video-interfaces.yaml#
0050 unevaluatedProperties: false
0051
0052 properties:
0053 bus-width:
0054 enum: [ 8, 10, 12, 16 ]
0055
0056 pclk-sample: true
0057 hsync-active: true
0058 vsync-active: true
0059
0060 required:
0061 - bus-width
0062
0063 unevaluatedProperties: false
0064
0065 ports:
0066 $ref: /schemas/graph.yaml#/properties/ports
0067
0068 properties:
0069 port@0:
0070 $ref: "#/properties/port"
0071
0072 port@1:
0073 $ref: /schemas/graph.yaml#/properties/port
0074 description: MIPI CSI-2 bridge input port
0075
0076 anyOf:
0077 - required:
0078 - port@0
0079 - required:
0080 - port@1
0081
0082 required:
0083 - compatible
0084 - reg
0085 - interrupts
0086 - clocks
0087 - clock-names
0088 - resets
0089
0090 oneOf:
0091 - required:
0092 - ports
0093 - required:
0094 - port
0095
0096 additionalProperties: false
0097
0098 examples:
0099 - |
0100 #include <dt-bindings/interrupt-controller/arm-gic.h>
0101 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
0102 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
0103
0104 csi1: csi@1cb4000 {
0105 compatible = "allwinner,sun8i-v3s-csi";
0106 reg = <0x01cb4000 0x1000>;
0107 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0108 clocks = <&ccu CLK_BUS_CSI>,
0109 <&ccu CLK_CSI1_SCLK>,
0110 <&ccu CLK_DRAM_CSI>;
0111 clock-names = "bus",
0112 "mod",
0113 "ram";
0114 resets = <&ccu RST_BUS_CSI>;
0115
0116 ports {
0117 #address-cells = <1>;
0118 #size-cells = <0>;
0119
0120 port@0 {
0121 reg = <0>;
0122 /* Parallel bus endpoint */
0123 csi1_ep: endpoint {
0124 remote-endpoint = <&adv7611_ep>;
0125 bus-width = <16>;
0126
0127 /*
0128 * If hsync-active/vsync-active are missing,
0129 * embedded BT.656 sync is used.
0130 */
0131 hsync-active = <0>; /* Active low */
0132 vsync-active = <0>; /* Active low */
0133 pclk-sample = <1>; /* Rising */
0134 };
0135 };
0136 };
0137 };
0138
0139 ...
