0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A10 Video Engine Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 properties:
0014 compatible:
0015 enum:
0016 - allwinner,sun4i-a10-video-engine
0017 - allwinner,sun5i-a13-video-engine
0018 - allwinner,sun7i-a20-video-engine
0019 - allwinner,sun8i-a33-video-engine
0020 - allwinner,sun8i-h3-video-engine
0021 - allwinner,sun8i-v3s-video-engine
0022 - allwinner,sun8i-r40-video-engine
0023 - allwinner,sun20i-d1-video-engine
0024 - allwinner,sun50i-a64-video-engine
0025 - allwinner,sun50i-h5-video-engine
0026 - allwinner,sun50i-h6-video-engine
0027
0028 reg:
0029 maxItems: 1
0030
0031 interrupts:
0032 maxItems: 1
0033
0034 clocks:
0035 items:
0036 - description: Bus Clock
0037 - description: Module Clock
0038 - description: RAM Clock
0039
0040 clock-names:
0041 items:
0042 - const: ahb
0043 - const: mod
0044 - const: ram
0045
0046 resets:
0047 maxItems: 1
0048
0049 allwinner,sram:
0050 $ref: /schemas/types.yaml#/definitions/phandle-array
0051 items:
0052 - items:
0053 - description: phandle to SRAM
0054 - description: register value for device
0055 description: Phandle to the device SRAM
0056
0057 iommus:
0058 maxItems: 1
0059
0060 memory-region:
0061 maxItems: 1
0062 description:
0063 CMA pool to use for buffers allocation instead of the default
0064 CMA pool.
0065
0066 required:
0067 - compatible
0068 - reg
0069 - interrupts
0070 - clocks
0071 - clock-names
0072 - resets
0073 - allwinner,sram
0074
0075 additionalProperties: false
0076
0077 examples:
0078 - |
0079 #include <dt-bindings/interrupt-controller/arm-gic.h>
0080 #include <dt-bindings/clock/sun7i-a20-ccu.h>
0081 #include <dt-bindings/reset/sun4i-a10-ccu.h>
0082
0083 video-codec@1c0e000 {
0084 compatible = "allwinner,sun7i-a20-video-engine";
0085 reg = <0x01c0e000 0x1000>;
0086 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0087 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
0088 <&ccu CLK_DRAM_VE>;
0089 clock-names = "ahb", "mod", "ram";
0090 resets = <&ccu RST_VE>;
0091 allwinner,sram = <&ve_sram 1>;
0092 };
0093
0094 ...
