0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/media/allegro,al5e.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allegro DVT Video IP Codecs Device Tree Bindings
0008
0009 maintainers:
0010 - Michael Tretter <m.tretter@pengutronix.de>
0011
0012 description: |-
0013 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
0014 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
0015
0016 Each actual codec engine is controlled by a microcontroller (MCU). Host
0017 software uses a provided mailbox interface to communicate with the MCU. The
0018 MCUs share an interrupt.
0019
0020 properties:
0021 compatible:
0022 oneOf:
0023 - items:
0024 - const: allegro,al5e-1.1
0025 - const: allegro,al5e
0026 - items:
0027 - const: allegro,al5d-1.1
0028 - const: allegro,al5d
0029
0030 reg:
0031 items:
0032 - description: The registers
0033 - description: The SRAM
0034
0035 reg-names:
0036 items:
0037 - const: regs
0038 - const: sram
0039
0040 interrupts:
0041 maxItems: 1
0042
0043 clocks:
0044 items:
0045 - description: Core clock
0046 - description: MCU clock
0047 - description: Core AXI master port clock
0048 - description: MCU AXI master port clock
0049 - description: AXI4-Lite slave port clock
0050
0051 clock-names:
0052 items:
0053 - const: core_clk
0054 - const: mcu_clk
0055 - const: m_axi_core_aclk
0056 - const: m_axi_mcu_aclk
0057 - const: s_axi_lite_aclk
0058
0059 required:
0060 - compatible
0061 - reg
0062 - reg-names
0063 - interrupts
0064 - clocks
0065 - clock-names
0066
0067 additionalProperties: False
0068
0069 examples:
0070 - |
0071 fpga {
0072 #address-cells = <2>;
0073 #size-cells = <2>;
0074
0075 al5e: video-codec@a0009000 {
0076 compatible = "allegro,al5e-1.1", "allegro,al5e";
0077 reg = <0 0xa0009000 0 0x1000>,
0078 <0 0xa0000000 0 0x8000>;
0079 reg-names = "regs", "sram";
0080 interrupts = <0 96 4>;
0081 clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,
0082 <&clkc 71>, <&clkc 71>, <&clkc 71>;
0083 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
0084 "m_axi_mcu_aclk", "s_axi_lite_aclk";
0085 };
0086 };
0087 - |
0088 fpga {
0089 #address-cells = <2>;
0090 #size-cells = <2>;
0091
0092 al5d: video-codec@a0029000 {
0093 compatible = "allegro,al5d-1.1", "allegro,al5d";
0094 reg = <0 0xa0029000 0 0x1000>,
0095 <0 0xa0020000 0 0x8000>;
0096 reg-names = "regs", "sram";
0097 interrupts = <0 96 4>;
0098 clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>,
0099 <&clkc 71>, <&clkc 71>, <&clkc 71>;
0100 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
0101 "m_axi_mcu_aclk", "s_axi_lite_aclk";
0102 };
0103 };
0104
0105 ...
