0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: STMicroelectronics STM32 IPC controller bindings
0008
0009 description:
0010 The IPCC block provides a non blocking signaling mechanism to post and
0011 retrieve messages in an atomic way between two processors.
0012 It provides the signaling for N bidirectionnal channels. The number of
0013 channels (N) can be read from a dedicated register.
0014
0015 maintainers:
0016 - Fabien Dessenne <fabien.dessenne@foss.st.com>
0017 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
0018
0019 properties:
0020 compatible:
0021 const: st,stm32mp1-ipcc
0022
0023 reg:
0024 maxItems: 1
0025
0026 clocks:
0027 maxItems: 1
0028
0029 interrupts:
0030 items:
0031 - description: rx channel occupied
0032 - description: tx channel free
0033
0034 interrupt-names:
0035 items:
0036 - const: rx
0037 - const: tx
0038
0039 wakeup-source: true
0040
0041 "#mbox-cells":
0042 const: 1
0043
0044 st,proc-id:
0045 description: Processor id using the mailbox (0 or 1)
0046 $ref: /schemas/types.yaml#/definitions/uint32
0047 enum: [0, 1]
0048
0049 required:
0050 - compatible
0051 - reg
0052 - st,proc-id
0053 - clocks
0054 - interrupt-names
0055 - "#mbox-cells"
0056 - interrupts
0057
0058 additionalProperties: false
0059
0060 examples:
0061 - |
0062 #include <dt-bindings/interrupt-controller/arm-gic.h>
0063 #include <dt-bindings/clock/stm32mp1-clks.h>
0064 ipcc: mailbox@4c001000 {
0065 compatible = "st,stm32mp1-ipcc";
0066 #mbox-cells = <1>;
0067 reg = <0x4c001000 0x400>;
0068 st,proc-id = <0>;
0069 interrupts-extended = <&exti 61 1>,
0070 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0071 interrupt-names = "rx", "tx";
0072 clocks = <&rcc_clk IPCC>;
0073 wakeup-source;
0074 };
0075
0076 ...
