0001 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
0008
0009 maintainers:
0010 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0011
0012 description:
0013 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
0014 to route interrupts across various subsystems. It involves a three-level
0015 addressing scheme called protocol, client and signal. For example, consider an
0016 entity on the Application Processor Subsystem (APSS) that wants to listen to
0017 Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
0018 a case, the client would be Modem (client-id is 2) and the signal would be
0019 SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
0020 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
0021 for the list of such IDs.
0022
0023 properties:
0024 compatible:
0025 items:
0026 - enum:
0027 - qcom,sm6350-ipcc
0028 - qcom,sm6375-ipcc
0029 - qcom,sm8250-ipcc
0030 - qcom,sm8350-ipcc
0031 - qcom,sm8450-ipcc
0032 - qcom,sc7280-ipcc
0033 - const: qcom,ipcc
0034
0035 reg:
0036 maxItems: 1
0037
0038 interrupts:
0039 maxItems: 1
0040
0041 interrupt-controller: true
0042
0043 "#interrupt-cells":
0044 const: 3
0045 description:
0046 The first cell is the client-id, the second cell is the signal-id and the
0047 third cell is the interrupt type.
0048
0049 "#mbox-cells":
0050 const: 2
0051 description:
0052 The first cell is the client-id, and the second cell is the signal-id.
0053
0054 required:
0055 - compatible
0056 - reg
0057 - interrupts
0058 - interrupt-controller
0059 - "#interrupt-cells"
0060 - "#mbox-cells"
0061
0062 additionalProperties: false
0063
0064 examples:
0065 - |
0066 #include <dt-bindings/interrupt-controller/arm-gic.h>
0067 #include <dt-bindings/mailbox/qcom-ipcc.h>
0068
0069 mailbox@408000 {
0070 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
0071 reg = <0x408000 0x1000>;
0072 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
0073 interrupt-controller;
0074 #interrupt-cells = <3>;
0075 #mbox-cells = <2>;
0076 };
