0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 description: |
0014 The HSP modules are used for the processors to share resources and
0015 communicate together. It provides a set of hardware synchronization
0016 primitives for interprocessor communication. So the interprocessor
0017 communication (IPC) protocols can use hardware synchronization
0018 primitives, when operating between two processors not in an SMP
0019 relationship.
0020
0021 The features that HSP supported are shared mailboxes, shared
0022 semaphores, arbitrated semaphores and doorbells.
0023
0024 The mbox specifier of the "mboxes" property in the client node should
0025 contain two cells. The first cell determines the HSP type and the
0026 second cell is used to identify the mailbox that the client is going
0027 to use.
0028
0029 For shared mailboxes, the first cell composed of two fields:
0030 - bits 15..8:
0031 A bit mask of flags that further specifies the type of shared
0032 mailbox to be used (based on the data size). If no flag is
0033 specified then, 32-bit shared mailbox is used.
0034 - bits 7..0:
0035 Defines the type of the mailbox to be used. This field should be
0036 TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes.
0037
0038 For doorbells, the second cell specifies the index of the doorbell to
0039 use.
0040
0041 For shared mailboxes, the second cell is composed of two fields:
0042 - bits 31..24:
0043 A bit mask of flags that further specify how the shared mailbox
0044 will be used. Valid flags are:
0045 - bit 31:
0046 Defines the direction of the mailbox. If set, the mailbox
0047 will be used as a producer (i.e. used to send data). If
0048 cleared, the mailbox is the consumer of data sent by a
0049 producer.
0050
0051 - bits 23..0:
0052 The index of the shared mailbox to use. The number of available
0053 mailboxes may vary by instance of the HSP block and SoC
0054 generation.
0055
0056 The following file contains definitions that can be used to
0057 construct mailbox specifiers:
0058
0059 <dt-bindings/mailbox/tegra186-hsp.h>
0060
0061 properties:
0062 $nodename:
0063 pattern: "^hsp@[0-9a-f]+$"
0064
0065 compatible:
0066 oneOf:
0067 - const: nvidia,tegra186-hsp
0068 - const: nvidia,tegra194-hsp
0069 - items:
0070 - const: nvidia,tegra234-hsp
0071 - const: nvidia,tegra194-hsp
0072
0073 reg:
0074 maxItems: 1
0075
0076 interrupts:
0077 minItems: 1
0078 maxItems: 9
0079
0080 interrupt-names:
0081 oneOf:
0082 # shared interrupts are optional
0083 - items:
0084 - const: doorbell
0085
0086 - items:
0087 - const: doorbell
0088 - pattern: "^shared[0-7]$"
0089 - pattern: "^shared[0-7]$"
0090 - pattern: "^shared[0-7]$"
0091 - pattern: "^shared[0-7]$"
0092 - pattern: "^shared[0-7]$"
0093 - pattern: "^shared[0-7]$"
0094 - pattern: "^shared[0-7]$"
0095 - pattern: "^shared[0-7]$"
0096
0097 - items:
0098 - pattern: "^shared[0-7]$"
0099 - pattern: "^shared[0-7]$"
0100 - pattern: "^shared[0-7]$"
0101 - pattern: "^shared[0-7]$"
0102
0103 "#mbox-cells":
0104 const: 2
0105
0106 additionalProperties: false
0107
0108 examples:
0109 - |
0110 #include <dt-bindings/interrupt-controller/arm-gic.h>
0111 #include <dt-bindings/mailbox/tegra186-hsp.h>
0112
0113 hsp_top0: hsp@3c00000 {
0114 compatible = "nvidia,tegra186-hsp";
0115 reg = <0x03c00000 0xa0000>;
0116 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
0117 interrupt-names = "doorbell";
0118 #mbox-cells = <2>;
0119 };
0120
0121 client {
0122 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
0123 };
