0001 MediaTek GCE
0002 ===============
0003
0004 The Global Command Engine (GCE) is used to help read/write registers with
0005 critical time limitation, such as updating display configuration during the
0006 vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
0007
0008 CMDQ driver uses mailbox framework for communication. Please refer to
0009 mailbox.txt for generic information about mailbox device-tree bindings.
0010
0011 Required properties:
0012 - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce",
0013 "mediatek,mt8186-gce", "mediatek,mt8192-gce", "mediatek,mt8195-gce" or
0014 "mediatek,mt6779-gce".
0015 - reg: Address range of the GCE unit
0016 - interrupts: The interrupt signal from the GCE block
0017 - clock: Clocks according to the common clock binding
0018 - clock-names: Must be "gce" to stand for GCE clock
0019 - #mbox-cells: Should be 2.
0020 <&phandle channel priority>
0021 phandle: Label name of a gce node.
0022 channel: Channel of mailbox. Be equal to the thread id of GCE.
0023 priority: Priority of GCE thread.
0024
0025 Required properties for a client device:
0026 - mboxes: Client use mailbox to communicate with GCE, it should have this
0027 property and list of phandle, mailbox specifiers.
0028 Optional properties for a client device:
0029 - mediatek,gce-client-reg: Specify the sub-system id which is corresponding
0030 to the register address, it should have this property and list of phandle,
0031 sub-system specifiers.
0032 <&phandle subsys_number start_offset size>
0033 phandle: Label name of a gce node.
0034 subsys_number: specify the sub-system id which is corresponding
0035 to the register address.
0036 start_offset: the start offset of register address that GCE can access.
0037 size: the total size of register address that GCE can access.
0038
0039 Optional properties for a client mutex node:
0040 - mediatek,gce-events: GCE events used by clients. The event numbers are
0041 defined in 'dt-bindings/gce/<chip>-gce.h'.
0042
0043 Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
0044 'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8186-gce.h'
0045 'dt-bindings/gce/mt8192-gce.h', 'dt-bindings/gce/mt8195-gce.h' or
0046 'dt-bindings/gce/mt6779-gce.h'.
0047 Such as sub-system ids, thread priority, event ids.
0048
0049 Example:
0050
0051 gce: gce@10212000 {
0052 compatible = "mediatek,mt8173-gce";
0053 reg = <0 0x10212000 0 0x1000>;
0054 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
0055 clocks = <&infracfg CLK_INFRA_GCE>;
0056 clock-names = "gce";
0057 #mbox-cells = <2>;
0058 };
0059
0060 Example for a client device:
0061
0062 mmsys: clock-controller@14000000 {
0063 compatible = "mediatek,mt8173-mmsys";
0064 mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST>,
0065 <&gce 1 CMDQ_THR_PRIO_LOWEST>;
0066 mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
0067 CMDQ_EVENT_MUTEX1_STREAM_EOF>;
0068 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
0069 <&gce SUBSYS_1401XXXX 0x2000 0x100>;
0070 ...
0071 };
0072
0073 Example for a client mutex node:
0074 mutex: mutex@14020000 {
0075 compatible = "mediatek,mt8173-disp-mutex";
0076 reg = <0 0x14020000 0 0x1000>;
0077 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
0078 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0079 clocks = <&mmsys CLK_MM_MUTEX_32K>;
0080 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
0081 <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
0082 };
