0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX Messaging Unit (MU)
0008
0009 maintainers:
0010 - Dong Aisheng <aisheng.dong@nxp.com>
0011
0012 description: |
0013 The Messaging Unit module enables two processors within the SoC to
0014 communicate and coordinate by passing messages (e.g. data, status
0015 and control) through the MU interface. The MU also provides the ability
0016 for one processor to signal the other processor using interrupts.
0017
0018 Because the MU manages the messaging between processors, the MU uses
0019 different clocks (from each side of the different peripheral buses).
0020 Therefore, the MU must synchronize the accesses from one side to the
0021 other. The MU accomplishes synchronization using two sets of matching
0022 registers (Processor A-facing, Processor B-facing).
0023
0024 properties:
0025 compatible:
0026 oneOf:
0027 - const: fsl,imx6sx-mu
0028 - const: fsl,imx7ulp-mu
0029 - const: fsl,imx8ulp-mu
0030 - const: fsl,imx8-mu-scu
0031 - const: fsl,imx8-mu-seco
0032 - const: fsl,imx93-mu-s4
0033 - const: fsl,imx8ulp-mu-s4
0034 - items:
0035 - const: fsl,imx93-mu
0036 - const: fsl,imx8ulp-mu
0037 - items:
0038 - enum:
0039 - fsl,imx7s-mu
0040 - fsl,imx8mq-mu
0041 - fsl,imx8mm-mu
0042 - fsl,imx8mn-mu
0043 - fsl,imx8mp-mu
0044 - fsl,imx8qm-mu
0045 - fsl,imx8qxp-mu
0046 - const: fsl,imx6sx-mu
0047 - description: To communicate with i.MX8 SCU with fast IPC
0048 items:
0049 - const: fsl,imx8-mu-scu
0050 - enum:
0051 - fsl,imx8qm-mu
0052 - fsl,imx8qxp-mu
0053 - const: fsl,imx6sx-mu
0054
0055 reg:
0056 maxItems: 1
0057
0058 interrupts:
0059 minItems: 1
0060 maxItems: 2
0061
0062 interrupt-names:
0063 minItems: 1
0064 items:
0065 - const: tx
0066 - const: rx
0067
0068 "#mbox-cells":
0069 description: |
0070 <&phandle type channel>
0071 phandle : Label name of controller
0072 type : Channel type
0073 channel : Channel number
0074
0075 This MU support 5 type of unidirectional channels, each type
0076 has 4 channels except RST channel which only has 1 channel.
0077 A total of 17 channels. Following types are
0078 supported:
0079 0 - TX channel with 32bit transmit register and IRQ transmit
0080 acknowledgment support.
0081 1 - RX channel with 32bit receive register and IRQ support
0082 2 - TX doorbell channel. Without own register and no ACK support.
0083 3 - RX doorbell channel.
0084 4 - RST channel
0085 const: 2
0086
0087 clocks:
0088 maxItems: 1
0089
0090 fsl,mu-side-b:
0091 description: boolean, if present, means it is for side B MU.
0092 type: boolean
0093
0094 power-domains:
0095 maxItems: 1
0096
0097 required:
0098 - compatible
0099 - reg
0100 - interrupts
0101 - "#mbox-cells"
0102
0103 allOf:
0104 - if:
0105 properties:
0106 compatible:
0107 enum:
0108 - fsl,imx93-mu-s4
0109 then:
0110 properties:
0111 interrupt-names:
0112 minItems: 2
0113 interrupts:
0114 minItems: 2
0115
0116 else:
0117 properties:
0118 interrupts:
0119 maxItems: 1
0120 not:
0121 required:
0122 - interrupt-names
0123
0124 additionalProperties: false
0125
0126 examples:
0127 - |
0128 #include <dt-bindings/interrupt-controller/arm-gic.h>
0129
0130 mailbox@5d1b0000 {
0131 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
0132 reg = <0x5d1b0000 0x10000>;
0133 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
0134 #mbox-cells = <2>;
0135 };
