0001 Broadcom FlexRM Ring Manager
0002 ============================
0003 The Broadcom FlexRM ring manager provides a set of rings which can be
0004 used to submit work to offload engines. An SoC may have multiple FlexRM
0005 hardware blocks. There is one device tree entry per FlexRM block. The
0006 FlexRM driver will create a mailbox-controller instance for given FlexRM
0007 hardware block where each mailbox channel is a separate FlexRM ring.
0008
0009 Required properties:
0010 --------------------
0011 - compatible: Should be "brcm,iproc-flexrm-mbox"
0012 - reg: Specifies base physical address and size of the FlexRM
0013 ring registers
0014 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
0015 The FlexRM engine will send MSIs (instead of wired
0016 interrupts) to CPU. There is one MSI for each FlexRM ring.
0017 Refer devicetree/bindings/interrupt-controller/msi.txt
0018 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
0019 channel. This should be 3.
0020
0021 The 1st cell is the mailbox channel number.
0022
0023 The 2nd cell contains MSI completion threshold. This is the
0024 number of completion messages for which FlexRM will inject
0025 one MSI interrupt to CPU.
0026
0027 The 3nd cell contains MSI timer value representing time for
0028 which FlexRM will wait to accumulate N completion messages
0029 where N is the value specified by 2nd cell above. If FlexRM
0030 does not get required number of completion messages in time
0031 specified by this cell then it will inject one MSI interrupt
0032 to CPU provided atleast one completion message is available.
0033
0034 Optional properties:
0035 --------------------
0036 - dma-coherent: Present if DMA operations made by the FlexRM engine (such
0037 as DMA descriptor access, access to buffers pointed by DMA
0038 descriptors and read/write pointer updates to DDR) are
0039 cache coherent with the CPU.
0040
0041 Example:
0042 --------
0043 crypto_mbox: mbox@67000000 {
0044 compatible = "brcm,iproc-flexrm-mbox";
0045 reg = <0x67000000 0x200000>;
0046 msi-parent = <&gic_its 0x7f00>;
0047 #mbox-cells = <3>;
0048 };
0049
0050 crypto@672c0000 {
0051 compatible = "brcm,spu2-v2-crypto";
0052 reg = <0x672c0000 0x1000>;
0053 mboxes = <&crypto_mbox 0 0x1 0xffff>,
0054 <&crypto_mbox 1 0x1 0xffff>,
0055 <&crypto_mbox 16 0x1 0xffff>,
0056 <&crypto_mbox 17 0x1 0xffff>,
0057 <&crypto_mbox 30 0x1 0xffff>,
0058 <&crypto_mbox 31 0x1 0xffff>;
0059 };
