0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner sunxi Message Box
0008
0009 maintainers:
0010 - Samuel Holland <samuel@sholland.org>
0011
0012 description: |
0013 The hardware message box on sun6i, sun8i, sun9i, and sun50i SoCs is a
0014 two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
0015 is raised for received messages, but software must poll to know when a
0016 transmitted message has been acknowledged by the remote user. Each FIFO can
0017 hold four 32-bit messages; when a FIFO is full, clients must wait before
0018 attempting more transmissions.
0019
0020 Refer to ./mailbox.txt for generic information about mailbox device-tree
0021 bindings.
0022
0023 properties:
0024 compatible:
0025 oneOf:
0026 - items:
0027 - enum:
0028 - allwinner,sun8i-a83t-msgbox
0029 - allwinner,sun8i-h3-msgbox
0030 - allwinner,sun9i-a80-msgbox
0031 - allwinner,sun50i-a64-msgbox
0032 - allwinner,sun50i-h6-msgbox
0033 - const: allwinner,sun6i-a31-msgbox
0034 - const: allwinner,sun6i-a31-msgbox
0035
0036 reg:
0037 maxItems: 1
0038
0039 clocks:
0040 maxItems: 1
0041 description: bus clock
0042
0043 resets:
0044 maxItems: 1
0045 description: bus reset
0046
0047 interrupts:
0048 maxItems: 1
0049
0050 '#mbox-cells':
0051 const: 1
0052 description: first cell is the channel number (0-7)
0053
0054 required:
0055 - compatible
0056 - reg
0057 - clocks
0058 - resets
0059 - interrupts
0060 - '#mbox-cells'
0061
0062 additionalProperties: false
0063
0064 examples:
0065 - |
0066 #include <dt-bindings/clock/sun8i-h3-ccu.h>
0067 #include <dt-bindings/interrupt-controller/arm-gic.h>
0068 #include <dt-bindings/reset/sun8i-h3-ccu.h>
0069
0070 msgbox: mailbox@1c17000 {
0071 compatible = "allwinner,sun8i-h3-msgbox",
0072 "allwinner,sun6i-a31-msgbox";
0073 reg = <0x01c17000 0x1000>;
0074 clocks = <&ccu CLK_BUS_MSGBOX>;
0075 resets = <&ccu RST_BUS_MSGBOX>;
0076 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0077 #mbox-cells = <1>;
0078 };
0079
0080 ...
