0001 OMAP2+ IOMMU
0002
0003 Required properties:
0004 - compatible : Should be one of,
0005 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
0006 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
0007 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
0008 "ti,dra7-iommu" for DRA7xx IOMMU instances
0009 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
0010 - reg : Address space for the configuration registers
0011 - interrupts : Interrupt specifier for the IOMMU instance
0012 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
0013 and needs no additional data in the pargs specifier. Please
0014 also refer to the generic bindings document for more info
0015 on this property,
0016 Documentation/devicetree/bindings/iommu/iommu.txt
0017
0018 Optional properties:
0019 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
0020 Should be either 8 or 32 (default: 32)
0021 - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
0022 back a bus error response on MMU faults.
0023 - ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM
0024 syscon node that contains the additional control
0025 register for enabling the MMU, and the MMU instance
0026 number (0-indexed) within the sub-system. This property
0027 is required for DSP IOMMU instances on DRA7xx SoCs. The
0028 instance number should be 0 for DSP MDMA MMUs and 1 for
0029 DSP EDMA MMUs.
0030
0031 Example:
0032 /* OMAP3 ISP MMU */
0033 mmu_isp: mmu@480bd400 {
0034 #iommu-cells = <0>;
0035 compatible = "ti,omap2-iommu";
0036 reg = <0x480bd400 0x80>;
0037 interrupts = <24>;
0038 ti,hwmods = "mmu_isp";
0039 ti,#tlb-entries = <8>;
0040 };
0041
0042 /* DRA74x DSP2 MMUs */
0043 mmu0_dsp2: mmu@41501000 {
0044 compatible = "ti,dra7-dsp-iommu";
0045 reg = <0x41501000 0x100>;
0046 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0047 ti,hwmods = "mmu0_dsp2";
0048 #iommu-cells = <0>;
0049 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
0050 };
0051
0052 mmu1_dsp2: mmu@41502000 {
0053 compatible = "ti,dra7-dsp-iommu";
0054 reg = <0x41502000 0x100>;
0055 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
0056 ti,hwmods = "mmu1_dsp2";
0057 #iommu-cells = <0>;
0058 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
0059 };
