0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
0008
0009 maintainers:
0010 - Marek Szyprowski <m.szyprowski@samsung.com>
0011
0012 description: |+
0013 Samsung's Exynos architecture contains System MMUs that enables scattered
0014 physical memory chunks visible as a contiguous region to DMA-capable peripheral
0015 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
0016
0017 System MMU is an IOMMU and supports identical translation table format to
0018 ARMv7 translation tables with minimum set of page properties including access
0019 permissions, shareability and security protection. In addition, System MMU has
0020 another capabilities like L2 TLB or block-fetch buffers to minimize translation
0021 latency.
0022
0023 System MMUs are in many to one relation with peripheral devices, i.e. single
0024 peripheral device might have multiple System MMUs (usually one for each bus
0025 master), but one System MMU can handle transactions from only one peripheral
0026 device. The relation between a System MMU and the peripheral device needs to be
0027 defined in device node of the peripheral device.
0028
0029 MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
0030 MMUs.
0031 * MFC has one System MMU on its left and right bus.
0032 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
0033 for window 1, 2 and 3.
0034 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
0035 the other System MMU on the write channel.
0036
0037 For information on assigning System MMU controller to its peripheral devices,
0038 see generic IOMMU bindings.
0039
0040 properties:
0041 compatible:
0042 const: samsung,exynos-sysmmu
0043
0044 reg:
0045 maxItems: 1
0046
0047 interrupts:
0048 maxItems: 1
0049
0050 clocks:
0051 minItems: 1
0052 maxItems: 2
0053
0054 clock-names:
0055 oneOf:
0056 - items:
0057 - const: sysmmu
0058 - items:
0059 - const: sysmmu
0060 - const: master
0061 - items:
0062 - const: aclk
0063 - const: pclk
0064
0065 "#iommu-cells":
0066 const: 0
0067
0068 power-domains:
0069 description: |
0070 Required if the System MMU is needed to gate its power.
0071 Please refer to the following document:
0072 Documentation/devicetree/bindings/power/pd-samsung.yaml
0073 maxItems: 1
0074
0075 required:
0076 - compatible
0077 - reg
0078 - interrupts
0079 - clocks
0080 - clock-names
0081 - "#iommu-cells"
0082
0083 additionalProperties: false
0084
0085 examples:
0086 - |
0087 #include <dt-bindings/clock/exynos5250.h>
0088
0089 sysmmu_gsc0: iommu@13e80000 {
0090 compatible = "samsung,exynos-sysmmu";
0091 reg = <0x13E80000 0x1000>;
0092 interrupt-parent = <&combiner>;
0093 interrupts = <2 0>;
0094 clock-names = "sysmmu", "master";
0095 clocks = <&clock CLK_SMMU_GSCL0>,
0096 <&clock CLK_GSCL0>;
0097 power-domains = <&pd_gsc>;
0098 #iommu-cells = <0>;
0099 };
