0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip IOMMU
0008
0009 maintainers:
0010 - Heiko Stuebner <heiko@sntech.de>
0011
0012 description: |+
0013 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
0014 its master device. Each slave device is bound to a single master device and
0015 shares its clocks, power domain and irq.
0016
0017 For information on assigning IOMMU controller to its peripheral devices,
0018 see generic IOMMU bindings.
0019
0020 properties:
0021 compatible:
0022 enum:
0023 - rockchip,iommu
0024 - rockchip,rk3568-iommu
0025
0026 reg:
0027 items:
0028 - description: configuration registers for MMU instance 0
0029 - description: configuration registers for MMU instance 1
0030 minItems: 1
0031
0032 interrupts:
0033 items:
0034 - description: interruption for MMU instance 0
0035 - description: interruption for MMU instance 1
0036 minItems: 1
0037
0038 clocks:
0039 items:
0040 - description: Core clock
0041 - description: Interface clock
0042
0043 clock-names:
0044 items:
0045 - const: aclk
0046 - const: iface
0047
0048 "#iommu-cells":
0049 const: 0
0050
0051 power-domains:
0052 maxItems: 1
0053
0054 rockchip,disable-mmu-reset:
0055 $ref: /schemas/types.yaml#/definitions/flag
0056 description: |
0057 Do not use the mmu reset operation.
0058 Some mmu instances may produce unexpected results
0059 when the reset operation is used.
0060
0061 required:
0062 - compatible
0063 - reg
0064 - interrupts
0065 - clocks
0066 - clock-names
0067 - "#iommu-cells"
0068
0069 additionalProperties: false
0070
0071 examples:
0072 - |
0073 #include <dt-bindings/clock/rk3399-cru.h>
0074 #include <dt-bindings/interrupt-controller/arm-gic.h>
0075
0076 vopl_mmu: iommu@ff940300 {
0077 compatible = "rockchip,iommu";
0078 reg = <0xff940300 0x100>;
0079 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0080 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
0081 clock-names = "aclk", "iface";
0082 #iommu-cells = <0>;
0083 };
