0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas VMSA-Compatible IOMMU
0008
0009 maintainers:
0010 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
0011
0012 description:
0013 The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
0014 It provides address translation for bus masters outside of the CPU, each
0015 connected to the IPMMU through a port called micro-TLB.
0016
0017 properties:
0018 compatible:
0019 oneOf:
0020 - items:
0021 - enum:
0022 - renesas,ipmmu-r8a73a4 # R-Mobile APE6
0023 - renesas,ipmmu-r8a7742 # RZ/G1H
0024 - renesas,ipmmu-r8a7743 # RZ/G1M
0025 - renesas,ipmmu-r8a7744 # RZ/G1N
0026 - renesas,ipmmu-r8a7745 # RZ/G1E
0027 - renesas,ipmmu-r8a7790 # R-Car H2
0028 - renesas,ipmmu-r8a7791 # R-Car M2-W
0029 - renesas,ipmmu-r8a7793 # R-Car M2-N
0030 - renesas,ipmmu-r8a7794 # R-Car E2
0031 - const: renesas,ipmmu-vmsa # R-Mobile APE6 or R-Car Gen2 or RZ/G1
0032 - items:
0033 - enum:
0034 - renesas,ipmmu-r8a774a1 # RZ/G2M
0035 - renesas,ipmmu-r8a774b1 # RZ/G2N
0036 - renesas,ipmmu-r8a774c0 # RZ/G2E
0037 - renesas,ipmmu-r8a774e1 # RZ/G2H
0038 - renesas,ipmmu-r8a7795 # R-Car H3
0039 - renesas,ipmmu-r8a7796 # R-Car M3-W
0040 - renesas,ipmmu-r8a77961 # R-Car M3-W+
0041 - renesas,ipmmu-r8a77965 # R-Car M3-N
0042 - renesas,ipmmu-r8a77970 # R-Car V3M
0043 - renesas,ipmmu-r8a77980 # R-Car V3H
0044 - renesas,ipmmu-r8a77990 # R-Car E3
0045 - renesas,ipmmu-r8a77995 # R-Car D3
0046 - renesas,ipmmu-r8a779a0 # R-Car V3U
0047 - items:
0048 - enum:
0049 - renesas,ipmmu-r8a779f0 # R-Car S4-8
0050 - const: renesas,rcar-gen4-ipmmu-vmsa # R-Car Gen4
0051
0052 reg:
0053 maxItems: 1
0054
0055 interrupts:
0056 minItems: 1
0057 description:
0058 Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
0059 items:
0060 - description: non-secure mode
0061 - description: secure mode if supported
0062
0063 '#iommu-cells':
0064 const: 1
0065 description:
0066 The number of the micro-TLB that the device is connected to.
0067
0068 power-domains:
0069 maxItems: 1
0070
0071 renesas,ipmmu-main:
0072 $ref: /schemas/types.yaml#/definitions/phandle-array
0073 items:
0074 - items:
0075 - description: phandle to main IPMMU
0076 - description: the interrupt bit number associated with the particular
0077 cache IPMMU device. The interrupt bit number needs to match the main
0078 IPMMU IMSSTR register. Only used by cache IPMMU instances.
0079 description:
0080 Reference to the main IPMMU phandle plus 1 cell. The cell is
0081 the interrupt bit number associated with the particular cache IPMMU
0082 device. The interrupt bit number needs to match the main IPMMU IMSSTR
0083 register. Only used by cache IPMMU instances.
0084
0085 required:
0086 - compatible
0087 - reg
0088 - '#iommu-cells'
0089
0090 oneOf:
0091 - required:
0092 - interrupts
0093 - required:
0094 - renesas,ipmmu-main
0095
0096 additionalProperties: false
0097
0098 allOf:
0099 - if:
0100 properties:
0101 compatible:
0102 not:
0103 contains:
0104 const: renesas,ipmmu-vmsa
0105 then:
0106 required:
0107 - power-domains
0108
0109 examples:
0110 - |
0111 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
0112 #include <dt-bindings/interrupt-controller/arm-gic.h>
0113 #include <dt-bindings/power/r8a7791-sysc.h>
0114
0115 ipmmu_mx: iommu@fe951000 {
0116 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
0117 reg = <0xfe951000 0x1000>;
0118 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
0119 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0120 #iommu-cells = <1>;
0121 };
