0001 * QCOM IOMMU v1 Implementation
0002
0003 Qualcomm "B" family devices which are not compatible with arm-smmu have
0004 a similar looking IOMMU but without access to the global register space,
0005 and optionally requiring additional configuration to route context irqs
0006 to non-secure vs secure interrupt line.
0007
0008 ** Required properties:
0009
0010 - compatible : Should be one of:
0011
0012 "qcom,msm8916-iommu"
0013
0014 Followed by "qcom,msm-iommu-v1".
0015
0016 - clock-names : Should be a pair of "iface" (required for IOMMUs
0017 register group access) and "bus" (required for
0018 the IOMMUs underlying bus access).
0019
0020 - clocks : Phandles for respective clocks described by
0021 clock-names.
0022
0023 - #address-cells : must be 1.
0024
0025 - #size-cells : must be 1.
0026
0027 - #iommu-cells : Must be 1. Index identifies the context-bank #.
0028
0029 - ranges : Base address and size of the iommu context banks.
0030
0031 - qcom,iommu-secure-id : secure-id.
0032
0033 - List of sub-nodes, one per translation context bank. Each sub-node
0034 has the following required properties:
0035
0036 - compatible : Should be one of:
0037 - "qcom,msm-iommu-v1-ns" : non-secure context bank
0038 - "qcom,msm-iommu-v1-sec" : secure context bank
0039 - reg : Base address and size of context bank within the iommu
0040 - interrupts : The context fault irq.
0041
0042 ** Optional properties:
0043
0044 - reg : Base address and size of the SMMU local base, should
0045 be only specified if the iommu requires configuration
0046 for routing of context bank irq's to secure vs non-
0047 secure lines. (Ie. if the iommu contains secure
0048 context banks)
0049
0050
0051 ** Examples:
0052
0053 apps_iommu: iommu@1e20000 {
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056 #iommu-cells = <1>;
0057 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
0058 ranges = <0 0x1e20000 0x40000>;
0059 reg = <0x1ef0000 0x3000>;
0060 clocks = <&gcc GCC_SMMU_CFG_CLK>,
0061 <&gcc GCC_APSS_TCU_CLK>;
0062 clock-names = "iface", "bus";
0063 qcom,iommu-secure-id = <17>;
0064
0065 // mdp_0:
0066 iommu-ctx@4000 {
0067 compatible = "qcom,msm-iommu-v1-ns";
0068 reg = <0x4000 0x1000>;
0069 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0070 };
0071
0072 // venus_ns:
0073 iommu-ctx@5000 {
0074 compatible = "qcom,msm-iommu-v1-sec";
0075 reg = <0x5000 0x1000>;
0076 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0077 };
0078 };
0079
0080 gpu_iommu: iommu@1f08000 {
0081 #address-cells = <1>;
0082 #size-cells = <1>;
0083 #iommu-cells = <1>;
0084 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
0085 ranges = <0 0x1f08000 0x10000>;
0086 clocks = <&gcc GCC_SMMU_CFG_CLK>,
0087 <&gcc GCC_GFX_TCU_CLK>;
0088 clock-names = "iface", "bus";
0089 qcom,iommu-secure-id = <18>;
0090
0091 // gfx3d_user:
0092 iommu-ctx@1000 {
0093 compatible = "qcom,msm-iommu-v1-ns";
0094 reg = <0x1000 0x1000>;
0095 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
0096 };
0097
0098 // gfx3d_priv:
0099 iommu-ctx@2000 {
0100 compatible = "qcom,msm-iommu-v1-ns";
0101 reg = <0x2000 0x1000>;
0102 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
0103 };
0104 };
0105
0106 ...
0107
0108 venus: video-codec@1d00000 {
0109 ...
0110 iommus = <&apps_iommu 5>;
0111 };
0112
0113 mdp: mdp@1a01000 {
0114 ...
0115 iommus = <&apps_iommu 4>;
0116 };
0117
0118 gpu@1c00000 {
0119 ...
0120 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
0121 };
