0001 NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
0002
0003 Required properties:
0004 - compatible : "nvidia,tegra30-smmu"
0005 - reg : Should contain 3 register banks(address and length) for each
0006 of the SMMU register blocks.
0007 - interrupts : Should contain MC General interrupt.
0008 - nvidia,#asids : # of ASIDs
0009 - dma-window : IOVA start address and length.
0010 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
0011
0012 Example:
0013 smmu {
0014 compatible = "nvidia,tegra30-smmu";
0015 reg = <0x7000f010 0x02c
0016 0x7000f1f0 0x010
0017 0x7000f228 0x05c>;
0018 nvidia,#asids = <4>; /* # of ASIDs */
0019 dma-window = <0 0x40000000>; /* IOVA start & length */
0020 nvidia,ahb = <&ahb>;
0021 };
