0001 * QCOM IOMMU
0002
0003 The MSM IOMMU is an implementation compatible with the ARM VMSA short
0004 descriptor page tables. It provides address translation for bus masters outside
0005 of the CPU, each connected to the IOMMU through a port called micro-TLB.
0006
0007 Required Properties:
0008
0009 - compatible: Must contain "qcom,apq8064-iommu".
0010 - reg: Base address and size of the IOMMU registers.
0011 - interrupts: Specifiers for the MMU fault interrupts. For instances that
0012 support secure mode two interrupts must be specified, for non-secure and
0013 secure mode, in that order. For instances that don't support secure mode a
0014 single interrupt must be specified.
0015 - #iommu-cells: The number of cells needed to specify the stream id. This
0016 is always 1.
0017 - qcom,ncb: The total number of context banks in the IOMMU.
0018 - clocks : List of clocks to be used during SMMU register access. See
0019 Documentation/devicetree/bindings/clock/clock-bindings.txt
0020 for information about the format. For each clock specified
0021 here, there must be a corresponding entry in clock-names
0022 (see below).
0023
0024 - clock-names : List of clock names corresponding to the clocks specified in
0025 the "clocks" property (above).
0026 Should be "smmu_pclk" for specifying the interface clock
0027 required for iommu's register accesses.
0028 Should be "smmu_clk" for specifying the functional clock
0029 required by iommu for bus accesses.
0030
0031 Each bus master connected to an IOMMU must reference the IOMMU in its device
0032 node with the following property:
0033
0034 - iommus: A reference to the IOMMU in multiple cells. The first cell is a
0035 phandle to the IOMMU and the second cell is the stream id.
0036 A single master device can be connected to more than one iommu
0037 and multiple contexts in each of the iommu. So multiple entries
0038 are required to list all the iommus and the stream ids that the
0039 master is connected to.
0040
0041 Example: mdp iommu and its bus master
0042
0043 mdp_port0: iommu@7500000 {
0044 compatible = "qcom,apq8064-iommu";
0045 #iommu-cells = <1>;
0046 clock-names =
0047 "smmu_pclk",
0048 "smmu_clk";
0049 clocks =
0050 <&mmcc SMMU_AHB_CLK>,
0051 <&mmcc MDP_AXI_CLK>;
0052 reg = <0x07500000 0x100000>;
0053 interrupts =
0054 <GIC_SPI 63 0>,
0055 <GIC_SPI 64 0>;
0056 qcom,ncb = <2>;
0057 };
0058
0059 mdp: qcom,mdp@5100000 {
0060 compatible = "qcom,mdp";
0061 ...
0062 iommus = <&mdp_port0 0
0063 &mdp_port0 2>;
0064 };
