0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MediaTek IOMMU Architecture Implementation
0008
0009 maintainers:
0010 - Yong Wu <yong.wu@mediatek.com>
0011
0012 description: |+
0013 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
0014 this M4U have two generations of HW architecture. Generation one uses flat
0015 pagetable, and only supports 4K size page mapping. Generation two uses the
0016 ARM Short-Descriptor translation table format for address translation.
0017
0018 About the M4U Hardware Block Diagram, please check below:
0019
0020 EMI (External Memory Interface)
0021 |
0022 m4u (Multimedia Memory Management Unit)
0023 |
0024 +--------+
0025 | |
0026 gals0-rx gals1-rx (Global Async Local Sync rx)
0027 | |
0028 | |
0029 gals0-tx gals1-tx (Global Async Local Sync tx)
0030 | | Some SoCs may have GALS.
0031 +--------+
0032 |
0033 SMI Common(Smart Multimedia Interface Common)
0034 |
0035 +----------------+-------
0036 | |
0037 | gals-rx There may be GALS in some larbs.
0038 | |
0039 | |
0040 | gals-tx
0041 | |
0042 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
0043 (display) (vdec)
0044 | |
0045 | |
0046 +-----+-----+ +----+----+
0047 | | | | | |
0048 | | |... | | | ... There are different ports in each larb.
0049 | | | | | |
0050 OVL0 RDMA0 WDMA0 MC PP VLD
0051
0052 As above, The Multimedia HW will go through SMI and M4U while it
0053 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
0054 smi local arbiter and smi common. It will control whether the Multimedia
0055 HW should go though the m4u for translation or bypass it and talk
0056 directly with EMI. And also SMI help control the power domain and clocks for
0057 each local arbiter.
0058
0059 Normally we specify a local arbiter(larb) for each multimedia HW
0060 like display, video decode, and camera. And there are different ports
0061 in each larb. Take a example, There are many ports like MC, PP, VLD in the
0062 video decode local arbiter, all these ports are according to the video HW.
0063
0064 In some SoCs, there may be a GALS(Global Async Local Sync) module between
0065 smi-common and m4u, and additional GALS module between smi-larb and
0066 smi-common. GALS can been seen as a "asynchronous fifo" which could help
0067 synchronize for the modules in different clock frequency.
0068
0069 properties:
0070 compatible:
0071 oneOf:
0072 - enum:
0073 - mediatek,mt2701-m4u # generation one
0074 - mediatek,mt2712-m4u # generation two
0075 - mediatek,mt6779-m4u # generation two
0076 - mediatek,mt8167-m4u # generation two
0077 - mediatek,mt8173-m4u # generation two
0078 - mediatek,mt8183-m4u # generation two
0079 - mediatek,mt8186-iommu-mm # generation two
0080 - mediatek,mt8192-m4u # generation two
0081 - mediatek,mt8195-iommu-vdo # generation two
0082 - mediatek,mt8195-iommu-vpp # generation two
0083 - mediatek,mt8195-iommu-infra # generation two
0084
0085 - description: mt7623 generation one
0086 items:
0087 - const: mediatek,mt7623-m4u
0088 - const: mediatek,mt2701-m4u
0089
0090 reg:
0091 maxItems: 1
0092
0093 interrupts:
0094 maxItems: 1
0095
0096 clocks:
0097 items:
0098 - description: bclk is the block clock.
0099
0100 clock-names:
0101 items:
0102 - const: bclk
0103
0104 mediatek,infracfg:
0105 $ref: /schemas/types.yaml#/definitions/phandle
0106 description: The phandle to the mediatek infracfg syscon
0107
0108 mediatek,larbs:
0109 $ref: /schemas/types.yaml#/definitions/phandle-array
0110 minItems: 1
0111 maxItems: 32
0112 items:
0113 maxItems: 1
0114 description: |
0115 List of phandle to the local arbiters in the current Socs.
0116 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
0117 according to the local arbiter index, like larb0, larb1, larb2...
0118
0119 '#iommu-cells':
0120 const: 1
0121 description: |
0122 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
0123 defined in
0124 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
0125 dt-binding/memory/mt2712-larb-port.h for mt2712,
0126 dt-binding/memory/mt6779-larb-port.h for mt6779,
0127 dt-binding/memory/mt8167-larb-port.h for mt8167,
0128 dt-binding/memory/mt8173-larb-port.h for mt8173,
0129 dt-binding/memory/mt8183-larb-port.h for mt8183,
0130 dt-binding/memory/mt8186-memory-port.h for mt8186,
0131 dt-binding/memory/mt8192-larb-port.h for mt8192.
0132 dt-binding/memory/mt8195-memory-port.h for mt8195.
0133
0134 power-domains:
0135 maxItems: 1
0136
0137 required:
0138 - compatible
0139 - reg
0140 - interrupts
0141 - '#iommu-cells'
0142
0143 allOf:
0144 - if:
0145 properties:
0146 compatible:
0147 contains:
0148 enum:
0149 - mediatek,mt2701-m4u
0150 - mediatek,mt2712-m4u
0151 - mediatek,mt8173-m4u
0152 - mediatek,mt8186-iommu-mm
0153 - mediatek,mt8192-m4u
0154 - mediatek,mt8195-iommu-vdo
0155 - mediatek,mt8195-iommu-vpp
0156
0157 then:
0158 required:
0159 - clocks
0160
0161 - if:
0162 properties:
0163 compatible:
0164 enum:
0165 - mediatek,mt8186-iommu-mm
0166 - mediatek,mt8192-m4u
0167 - mediatek,mt8195-iommu-vdo
0168 - mediatek,mt8195-iommu-vpp
0169
0170 then:
0171 required:
0172 - power-domains
0173
0174 - if:
0175 properties:
0176 compatible:
0177 contains:
0178 enum:
0179 - mediatek,mt2712-m4u
0180 - mediatek,mt8173-m4u
0181
0182 then:
0183 required:
0184 - mediatek,infracfg
0185
0186 - if: # The IOMMUs don't have larbs.
0187 not:
0188 properties:
0189 compatible:
0190 contains:
0191 const: mediatek,mt8195-iommu-infra
0192
0193 then:
0194 required:
0195 - mediatek,larbs
0196
0197 additionalProperties: false
0198
0199 examples:
0200 - |
0201 #include <dt-bindings/clock/mt8173-clk.h>
0202 #include <dt-bindings/interrupt-controller/arm-gic.h>
0203
0204 iommu: iommu@10205000 {
0205 compatible = "mediatek,mt8173-m4u";
0206 reg = <0x10205000 0x1000>;
0207 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
0208 clocks = <&infracfg CLK_INFRA_M4U>;
0209 clock-names = "bclk";
0210 mediatek,infracfg = <&infracfg>;
0211 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
0212 <&larb3>, <&larb4>, <&larb5>;
0213 #iommu-cells = <1>;
0214 };
