0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM System MMU Architecture Implementation
0008
0009 maintainers:
0010 - Will Deacon <will@kernel.org>
0011 - Robin Murphy <Robin.Murphy@arm.com>
0012
0013 description: |+
0014 ARM SoCs may contain an implementation of the ARM System Memory
0015 Management Unit Architecture, which can be used to provide 1 or 2 stages
0016 of address translation to bus masters external to the CPU.
0017
0018 The SMMU may also raise interrupts in response to various fault
0019 conditions.
0020
0021 properties:
0022 $nodename:
0023 pattern: "^iommu@[0-9a-f]*"
0024 compatible:
0025 oneOf:
0026 - description: Qcom SoCs implementing "arm,smmu-v2"
0027 items:
0028 - enum:
0029 - qcom,msm8996-smmu-v2
0030 - qcom,msm8998-smmu-v2
0031 - const: qcom,smmu-v2
0032
0033 - description: Qcom SoCs implementing "arm,mmu-500"
0034 items:
0035 - enum:
0036 - qcom,qcm2290-smmu-500
0037 - qcom,sc7180-smmu-500
0038 - qcom,sc7280-smmu-500
0039 - qcom,sc8180x-smmu-500
0040 - qcom,sc8280xp-smmu-500
0041 - qcom,sdm845-smmu-500
0042 - qcom,sdx55-smmu-500
0043 - qcom,sdx65-smmu-500
0044 - qcom,sm6350-smmu-500
0045 - qcom,sm6375-smmu-500
0046 - qcom,sm8150-smmu-500
0047 - qcom,sm8250-smmu-500
0048 - qcom,sm8350-smmu-500
0049 - qcom,sm8450-smmu-500
0050 - const: arm,mmu-500
0051 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
0052 items:
0053 - enum:
0054 - qcom,sc7180-smmu-v2
0055 - qcom,sdm845-smmu-v2
0056 - const: qcom,adreno-smmu
0057 - const: qcom,smmu-v2
0058 - description: Marvell SoCs implementing "arm,mmu-500"
0059 items:
0060 - const: marvell,ap806-smmu-500
0061 - const: arm,mmu-500
0062 - description: NVIDIA SoCs that require memory controller interaction
0063 and may program multiple ARM MMU-500s identically with the memory
0064 controller interleaving translations between multiple instances
0065 for improved performance.
0066 items:
0067 - enum:
0068 - nvidia,tegra186-smmu
0069 - nvidia,tegra194-smmu
0070 - nvidia,tegra234-smmu
0071 - const: nvidia,smmu-500
0072 - items:
0073 - const: arm,mmu-500
0074 - const: arm,smmu-v2
0075 - items:
0076 - enum:
0077 - arm,mmu-400
0078 - arm,mmu-401
0079 - const: arm,smmu-v1
0080 - enum:
0081 - arm,smmu-v1
0082 - arm,smmu-v2
0083 - arm,mmu-400
0084 - arm,mmu-401
0085 - arm,mmu-500
0086 - cavium,smmu-v2
0087
0088 reg:
0089 minItems: 1
0090 maxItems: 2
0091
0092 '#global-interrupts':
0093 description: The number of global interrupts exposed by the device.
0094 $ref: /schemas/types.yaml#/definitions/uint32
0095 minimum: 0
0096 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
0097
0098 '#iommu-cells':
0099 enum: [ 1, 2 ]
0100 description: |
0101 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
0102 value of 1, each IOMMU specifier represents a distinct stream ID emitted
0103 by that device into the relevant SMMU.
0104
0105 SMMUs with stream matching support and complex masters may use a value of
0106 2, where the second cell of the IOMMU specifier represents an SMR mask to
0107 combine with the ID in the first cell. Care must be taken to ensure the
0108 set of matched IDs does not result in conflicts.
0109
0110 interrupts:
0111 minItems: 1
0112 maxItems: 388 # 260 plus 128 contexts
0113 description: |
0114 Interrupt list, with the first #global-interrupts entries corresponding to
0115 the global interrupts and any following entries corresponding to context
0116 interrupts, specified in order of their indexing by the SMMU.
0117
0118 For SMMUv2 implementations, there must be exactly one interrupt per
0119 context bank. In the case of a single, combined interrupt, it must be
0120 listed multiple times.
0121
0122 dma-coherent:
0123 description: |
0124 Present if page table walks made by the SMMU are cache coherent with the
0125 CPU.
0126
0127 NOTE: this only applies to the SMMU itself, not masters connected
0128 upstream of the SMMU.
0129
0130 calxeda,smmu-secure-config-access:
0131 type: boolean
0132 description:
0133 Enable proper handling of buggy implementations that always use secure
0134 access to SMMU configuration registers. In this case non-secure aliases of
0135 secure registers have to be used during SMMU configuration.
0136
0137 stream-match-mask:
0138 $ref: /schemas/types.yaml#/definitions/uint32
0139 description: |
0140 For SMMUs supporting stream matching and using #iommu-cells = <1>,
0141 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
0142 be programmed into the SMRn.MASK field of every stream match register
0143 used). For cases where it is desirable to ignore some portion of every
0144 Stream ID (e.g. for certain MMU-500 configurations given globally unique
0145 input IDs). This property is not valid for SMMUs using stream indexing, or
0146 using stream matching with #iommu-cells = <2>, and may be ignored if
0147 present in such cases.
0148
0149 clock-names:
0150 items:
0151 - const: bus
0152 - const: iface
0153
0154 clocks:
0155 items:
0156 - description: bus clock required for downstream bus access and for the
0157 smmu ptw
0158 - description: interface clock required to access smmu's registers
0159 through the TCU's programming interface.
0160
0161 power-domains:
0162 maxItems: 1
0163
0164 nvidia,memory-controller:
0165 description: |
0166 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
0167 The memory controller needs to be programmed with a mapping of memory
0168 client IDs to ARM SMMU stream IDs.
0169
0170 If this property is absent, the mapping programmed by early firmware
0171 will be used and it is not guaranteed that IOMMU translations will be
0172 enabled for any given device.
0173 $ref: /schemas/types.yaml#/definitions/phandle
0174
0175 required:
0176 - compatible
0177 - reg
0178 - '#global-interrupts'
0179 - '#iommu-cells'
0180 - interrupts
0181
0182 additionalProperties: false
0183
0184 allOf:
0185 - if:
0186 properties:
0187 compatible:
0188 contains:
0189 enum:
0190 - nvidia,tegra186-smmu
0191 - nvidia,tegra194-smmu
0192 - nvidia,tegra234-smmu
0193 then:
0194 properties:
0195 reg:
0196 minItems: 1
0197 maxItems: 2
0198
0199 # The reference to the memory controller is required to ensure that the
0200 # memory client to stream ID mapping can be done synchronously with the
0201 # IOMMU attachment.
0202 required:
0203 - nvidia,memory-controller
0204 else:
0205 properties:
0206 reg:
0207 maxItems: 1
0208
0209 examples:
0210 - |+
0211 /* SMMU with stream matching or stream indexing */
0212 smmu1: iommu@ba5e0000 {
0213 compatible = "arm,smmu-v1";
0214 reg = <0xba5e0000 0x10000>;
0215 #global-interrupts = <2>;
0216 interrupts = <0 32 4>,
0217 <0 33 4>,
0218 <0 34 4>, /* This is the first context interrupt */
0219 <0 35 4>,
0220 <0 36 4>,
0221 <0 37 4>;
0222 #iommu-cells = <1>;
0223 };
0224
0225 /* device with two stream IDs, 0 and 7 */
0226 master1 {
0227 iommus = <&smmu1 0>,
0228 <&smmu1 7>;
0229 };
0230
0231
0232 /* SMMU with stream matching */
0233 smmu2: iommu@ba5f0000 {
0234 compatible = "arm,smmu-v1";
0235 reg = <0xba5f0000 0x10000>;
0236 #global-interrupts = <2>;
0237 interrupts = <0 38 4>,
0238 <0 39 4>,
0239 <0 40 4>, /* This is the first context interrupt */
0240 <0 41 4>,
0241 <0 42 4>,
0242 <0 43 4>;
0243 #iommu-cells = <2>;
0244 };
0245
0246 /* device with stream IDs 0 and 7 */
0247 master2 {
0248 iommus = <&smmu2 0 0>,
0249 <&smmu2 7 0>;
0250 };
0251
0252 /* device with stream IDs 1, 17, 33 and 49 */
0253 master3 {
0254 iommus = <&smmu2 1 0x30>;
0255 };
0256
0257
0258 /* ARM MMU-500 with 10-bit stream ID input configuration */
0259 smmu3: iommu@ba600000 {
0260 compatible = "arm,mmu-500", "arm,smmu-v2";
0261 reg = <0xba600000 0x10000>;
0262 #global-interrupts = <2>;
0263 interrupts = <0 44 4>,
0264 <0 45 4>,
0265 <0 46 4>, /* This is the first context interrupt */
0266 <0 47 4>,
0267 <0 48 4>,
0268 <0 49 4>;
0269 #iommu-cells = <1>;
0270 /* always ignore appended 5-bit TBU number */
0271 stream-match-mask = <0x7c00>;
0272 };
0273
0274 bus {
0275 /* bus whose child devices emit one unique 10-bit stream
0276 ID each, but may master through multiple SMMU TBUs */
0277 iommu-map = <0 &smmu3 0 0x400>;
0278
0279
0280 };
0281
0282 - |+
0283 /* Qcom's arm,smmu-v2 implementation */
0284 #include <dt-bindings/interrupt-controller/arm-gic.h>
0285 #include <dt-bindings/interrupt-controller/irq.h>
0286 smmu4: iommu@d00000 {
0287 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
0288 reg = <0xd00000 0x10000>;
0289
0290 #global-interrupts = <1>;
0291 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
0292 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
0293 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
0294 #iommu-cells = <1>;
0295 power-domains = <&mmcc 0>;
0296
0297 clocks = <&mmcc 123>,
0298 <&mmcc 124>;
0299 clock-names = "bus", "iface";
0300 };
