0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM SMMUv3 Architecture Implementation
0008
0009 maintainers:
0010 - Will Deacon <will@kernel.org>
0011 - Robin Murphy <Robin.Murphy@arm.com>
0012
0013 description: |+
0014 The SMMUv3 architecture is a significant departure from previous
0015 revisions, replacing the MMIO register interface with in-memory command
0016 and event queues and adding support for the ATS and PRI components of
0017 the PCIe specification.
0018
0019 properties:
0020 $nodename:
0021 pattern: "^iommu@[0-9a-f]*"
0022 compatible:
0023 const: arm,smmu-v3
0024
0025 reg:
0026 maxItems: 1
0027
0028 interrupts:
0029 minItems: 1
0030 maxItems: 4
0031
0032 interrupt-names:
0033 oneOf:
0034 - const: combined
0035 description:
0036 The combined interrupt is optional, and should only be provided if the
0037 hardware supports just a single, combined interrupt line.
0038 If provided, then the combined interrupt will be used in preference to
0039 any others.
0040 - minItems: 1
0041 items:
0042 - enum:
0043 - eventq # Event Queue not empty
0044 - gerror # Global Error activated
0045 - const: gerror
0046 - enum:
0047 - cmdq-sync # CMD_SYNC complete
0048 - priq # PRI Queue not empty
0049 - enum:
0050 - cmdq-sync
0051 - priq
0052
0053 '#iommu-cells':
0054 const: 1
0055
0056 dma-coherent:
0057 description: |
0058 Present if page table walks made by the SMMU are cache coherent with the
0059 CPU.
0060
0061 NOTE: this only applies to the SMMU itself, not masters connected
0062 upstream of the SMMU.
0063
0064 msi-parent: true
0065
0066 hisilicon,broken-prefetch-cmd:
0067 type: boolean
0068 description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
0069
0070 cavium,cn9900-broken-page1-regspace:
0071 type: boolean
0072 description:
0073 Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
0074 register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
0075 doesn't support SMMU page1 register space.
0076
0077 required:
0078 - compatible
0079 - reg
0080 - '#iommu-cells'
0081
0082 additionalProperties: false
0083
0084 examples:
0085 - |+
0086 #include <dt-bindings/interrupt-controller/arm-gic.h>
0087 #include <dt-bindings/interrupt-controller/irq.h>
0088
0089 iommu@2b400000 {
0090 compatible = "arm,smmu-v3";
0091 reg = <0x2b400000 0x20000>;
0092 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
0093 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
0094 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
0095 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
0096 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
0097 dma-coherent;
0098 #iommu-cells = <1>;
0099 msi-parent = <&its 0xff0000>;
0100 };
