0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iommu/apple,dart.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Apple DART IOMMU
0008
0009 maintainers:
0010 - Sven Peter <sven@svenpeter.dev>
0011
0012 description: |+
0013 Apple SoCs may contain an implementation of their Device Address
0014 Resolution Table which provides a mandatory layer of address
0015 translations for various masters.
0016
0017 Each DART instance is capable of handling up to 16 different streams
0018 with individual pagetables and page-level read/write protection flags.
0019
0020 This DART IOMMU also raises interrupts in response to various
0021 fault conditions.
0022
0023 properties:
0024 compatible:
0025 const: apple,t8103-dart
0026
0027 reg:
0028 maxItems: 1
0029
0030 interrupts:
0031 maxItems: 1
0032
0033 clocks:
0034 description:
0035 Reference to the gate clock phandle if required for this IOMMU.
0036 Optional since not all IOMMUs are attached to a clock gate.
0037
0038 '#iommu-cells':
0039 const: 1
0040 description:
0041 Has to be one. The single cell describes the stream id emitted by
0042 a master to the IOMMU.
0043
0044 power-domains:
0045 maxItems: 1
0046
0047 required:
0048 - compatible
0049 - reg
0050 - '#iommu-cells'
0051 - interrupts
0052
0053 additionalProperties: false
0054
0055 examples:
0056 - |+
0057 dart1: iommu@82f80000 {
0058 compatible = "apple,t8103-dart";
0059 reg = <0x82f80000 0x4000>;
0060 interrupts = <1 781 4>;
0061 #iommu-cells = <1>;
0062 };
0063
0064 master1 {
0065 iommus = <&dart1 0>;
0066 };
0067
0068 - |+
0069 dart2a: iommu@82f00000 {
0070 compatible = "apple,t8103-dart";
0071 reg = <0x82f00000 0x4000>;
0072 interrupts = <1 781 4>;
0073 #iommu-cells = <1>;
0074 };
0075 dart2b: iommu@82f80000 {
0076 compatible = "apple,t8103-dart";
0077 reg = <0x82f80000 0x4000>;
0078 interrupts = <1 781 4>;
0079 #iommu-cells = <1>;
0080 };
0081
0082 master2 {
0083 iommus = <&dart2a 0>, <&dart2b 1>;
0084 };
