0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Texas Instruments K3 Interrupt Router
0008
0009 maintainers:
0010 - Lokesh Vutla <lokeshvutla@ti.com>
0011
0012 allOf:
0013 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
0014
0015 description: |
0016 The Interrupt Router (INTR) module provides a mechanism to mux M
0017 interrupt inputs to N interrupt outputs, where all M inputs are selectable
0018 to be driven per N output. An Interrupt Router can either handle edge
0019 triggered or level triggered interrupts and that is fixed in hardware.
0020
0021 Interrupt Router
0022 +----------------------+
0023 | Inputs Outputs |
0024 +-------+ | +------+ +-----+ |
0025 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
0026 +-------+ | +------+ +-----+ | controller
0027 | . . | +-------+
0028 +-------+ | . . |----->| IRQ |
0029 | INTA |----------->| . . | +-------+
0030 +-------+ | . +-----+ |
0031 | +------+ | N | |
0032 | | irqM | +-----+ |
0033 | +------+ |
0034 | |
0035 +----------------------+
0036
0037 There is one register per output (MUXCNTL_N) that controls the selection.
0038 Configuration of these MUXCNTL_N registers is done by a system controller
0039 (like the Device Memory and Security Controller on K3 AM654 SoC). System
0040 controller will keep track of the used and unused registers within the Router.
0041 Driver should request the system controller to get the range of GIC IRQs
0042 assigned to the requesting hosts. It is the drivers responsibility to keep
0043 track of Host IRQs.
0044
0045 Communication between the host processor running an OS and the system
0046 controller happens through a protocol called TI System Control Interface
0047 (TISCI protocol).
0048
0049 properties:
0050 compatible:
0051 const: ti,sci-intr
0052
0053 ti,intr-trigger-type:
0054 $ref: /schemas/types.yaml#/definitions/uint32
0055 enum: [1, 4]
0056 description: |
0057 Should be one of the following.
0058 1 = If intr supports edge triggered interrupts.
0059 4 = If intr supports level triggered interrupts.
0060
0061 interrupt-controller: true
0062
0063 '#interrupt-cells':
0064 const: 1
0065 description: |
0066 The 1st cell should contain interrupt router input hw number.
0067
0068 ti,interrupt-ranges:
0069 $ref: /schemas/types.yaml#/definitions/uint32-matrix
0070 description: |
0071 Interrupt ranges that converts the INTR output hw irq numbers
0072 to parents's input interrupt numbers.
0073 items:
0074 items:
0075 - description: |
0076 "output_irq" specifies the base for intr output irq
0077 - description: |
0078 "parent's input irq" specifies the base for parent irq
0079 - description: |
0080 "limit" specifies the limit for translation
0081
0082 required:
0083 - compatible
0084 - ti,intr-trigger-type
0085 - interrupt-controller
0086 - '#interrupt-cells'
0087 - ti,sci
0088 - ti,sci-dev-id
0089 - ti,interrupt-ranges
0090
0091 unevaluatedProperties: false
0092
0093 examples:
0094 - |
0095 main_gpio_intr: interrupt-controller0 {
0096 compatible = "ti,sci-intr";
0097 ti,intr-trigger-type = <1>;
0098 interrupt-controller;
0099 interrupt-parent = <&gic500>;
0100 #interrupt-cells = <1>;
0101 ti,sci = <&dmsc>;
0102 ti,sci-dev-id = <131>;
0103 ti,interrupt-ranges = <0 360 32>;
0104 };
