0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Texas Instruments K3 Interrupt Aggregator
0008
0009 maintainers:
0010 - Lokesh Vutla <lokeshvutla@ti.com>
0011
0012 allOf:
0013 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
0014
0015 description: |
0016 The Interrupt Aggregator (INTA) provides a centralized machine
0017 which handles the termination of system events to that they can
0018 be coherently processed by the host(s) in the system. A maximum
0019 of 64 events can be mapped to a single interrupt.
0020
0021 Interrupt Aggregator
0022 +-----------------------------------------+
0023 | Intmap VINT |
0024 | +--------------+ +------------+ |
0025 m ------>| | vint | bit | | 0 |.....|63| vint0 |
0026 . | +--------------+ +------------+ | +------+
0027 . | . . | | HOST |
0028 Globalevents ------>| . . |----->| IRQ |
0029 . | . . | | CTRL |
0030 . | . . | +------+
0031 n ------>| +--------------+ +------------+ |
0032 | | vint | bit | | 0 |.....|63| vintx |
0033 | +--------------+ +------------+ |
0034 | |
0035 | Unmap |
0036 | +--------------+ |
0037 Unmapped events ---->| | umapidx |-------------------------> Globalevents
0038 | +--------------+ |
0039 | |
0040 +-----------------------------------------+
0041
0042 Configuration of these Intmap registers that maps global events to vint is
0043 done by a system controller (like the Device Memory and Security Controller
0044 on AM654 SoC). Driver should request the system controller to get the range
0045 of global events and vints assigned to the requesting host. Management
0046 of these requested resources should be handled by driver and requests
0047 system controller to map specific global event to vint, bit pair.
0048
0049 Communication between the host processor running an OS and the system
0050 controller happens through a protocol called TI System Control Interface
0051 (TISCI protocol).
0052
0053 properties:
0054 compatible:
0055 const: ti,sci-inta
0056
0057 reg:
0058 maxItems: 1
0059
0060 interrupt-controller: true
0061
0062 msi-controller: true
0063
0064 ti,interrupt-ranges:
0065 $ref: /schemas/types.yaml#/definitions/uint32-matrix
0066 description: |
0067 Interrupt ranges that converts the INTA output hw irq numbers
0068 to parents's input interrupt numbers.
0069 items:
0070 items:
0071 - description: |
0072 "output_irq" specifies the base for inta output irq
0073 - description: |
0074 "parent's input irq" specifies the base for parent irq
0075 - description: |
0076 "limit" specifies the limit for translation
0077
0078 ti,unmapped-event-sources:
0079 $ref: /schemas/types.yaml#/definitions/phandle-array
0080 items:
0081 maxItems: 1
0082 description:
0083 Array of phandles to DMA controllers where the unmapped events originate.
0084
0085 required:
0086 - compatible
0087 - reg
0088 - interrupt-controller
0089 - msi-controller
0090 - ti,sci
0091 - ti,sci-dev-id
0092 - ti,interrupt-ranges
0093
0094 unevaluatedProperties: false
0095
0096 examples:
0097 - |
0098 bus {
0099 #address-cells = <2>;
0100 #size-cells = <2>;
0101
0102 main_udmass_inta: msi-controller@33d00000 {
0103 compatible = "ti,sci-inta";
0104 reg = <0x0 0x33d00000 0x0 0x100000>;
0105 interrupt-controller;
0106 msi-controller;
0107 interrupt-parent = <&main_navss_intr>;
0108 ti,sci = <&dmsc>;
0109 ti,sci-dev-id = <179>;
0110 ti,interrupt-ranges = <0 0 256>;
0111 };
0112 };
