0001 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: TI PRU-ICSS Local Interrupt Controller
0008
0009 maintainers:
0010 - Suman Anna <s-anna@ti.com>
0011
0012 description: |
0013 Each PRU-ICSS has a single interrupt controller instance that is common
0014 to all the PRU cores. Most interrupt controllers can route 64 input events
0015 which are then mapped to 10 possible output interrupts through two levels
0016 of mapping. The input events can be triggered by either the PRUs and/or
0017 various other PRUSS internal and external peripherals. The first 2 output
0018 interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
0019 remaining 8 (2 through 9) connected to external interrupt controllers
0020 including the MPU and/or other PRUSS instances, DSPs or devices.
0021
0022 The property "ti,irqs-reserved" is used for denoting the connection
0023 differences on the output interrupts 2 through 9. If this property is not
0024 defined, it implies that all the PRUSS INTC output interrupts 2 through 9
0025 (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt
0026 controller.
0027
0028 The K3 family of SoCs can handle 160 input events that can be mapped to 20
0029 different possible output interrupts. The additional output interrupts (10
0030 through 19) are connected to new sub-modules within the ICSSG instances.
0031
0032 This interrupt-controller node should be defined as a child node of the
0033 corresponding PRUSS node. The node should be named "interrupt-controller".
0034
0035 properties:
0036 $nodename:
0037 pattern: "^interrupt-controller@[0-9a-f]+$"
0038
0039 compatible:
0040 enum:
0041 - ti,pruss-intc
0042 - ti,icssg-intc
0043 description: |
0044 Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
0045 AM335x family of SoCs,
0046 AM437x family of SoCs,
0047 AM57xx family of SoCs
0048 66AK2G family of SoCs
0049 Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs
0050
0051 reg:
0052 maxItems: 1
0053
0054 interrupts:
0055 minItems: 1
0056 maxItems: 8
0057 description: |
0058 All the interrupts generated towards the main host processor in the SoC.
0059 A shared interrupt can be skipped if the desired destination and usage is
0060 by a different processor/device.
0061
0062 interrupt-names:
0063 minItems: 1
0064 maxItems: 8
0065 items:
0066 pattern: host_intr[0-7]
0067 description: |
0068 Should use one of the above names for each valid host event interrupt
0069 connected to Arm interrupt controller, the name should match the
0070 corresponding host event interrupt number.
0071
0072 interrupt-controller: true
0073
0074 "#interrupt-cells":
0075 const: 3
0076 description: |
0077 Client users shall use the PRU System event number (the interrupt source
0078 that the client is interested in) [cell 1], PRU channel [cell 2] and PRU
0079 host_event (target) [cell 3] as the value of the interrupts property in
0080 their node. The system events can be mapped to some output host
0081 interrupts through 2 levels of many-to-one mapping i.e. events to channel
0082 mapping and channels to host interrupts so through this property entire
0083 mapping is provided.
0084
0085 ti,irqs-reserved:
0086 $ref: /schemas/types.yaml#/definitions/uint8
0087 description: |
0088 Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
0089 output interrupts 2 through 9) that are not connected to the Arm interrupt
0090 controller or are shared and used by other devices or processors in the
0091 SoC. Define this property when any of 8 interrupts should not be handled
0092 by Arm interrupt controller.
0093 Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt
0094 connected to MPU
0095 - AM65x and J721E SoCs have "host_intr5", "host_intr6" and
0096 "host_intr7" interrupts connected to MPU, and other ICSSG
0097 instances.
0098 - AM64x SoCs have all the 8 host interrupts connected to various
0099 other SoC entities
0100
0101 required:
0102 - compatible
0103 - reg
0104 - interrupts
0105 - interrupt-names
0106 - interrupt-controller
0107 - "#interrupt-cells"
0108
0109 additionalProperties: false
0110
0111 examples:
0112 - |
0113 /* AM33xx PRU-ICSS */
0114 pruss: pruss@0 {
0115 compatible = "ti,am3356-pruss";
0116 reg = <0x0 0x80000>;
0117 #address-cells = <1>;
0118 #size-cells = <1>;
0119 ranges;
0120
0121 pruss_intc: interrupt-controller@20000 {
0122 compatible = "ti,pruss-intc";
0123 reg = <0x20000 0x2000>;
0124 interrupts = <20 21 22 23 24 25 26 27>;
0125 interrupt-names = "host_intr0", "host_intr1",
0126 "host_intr2", "host_intr3",
0127 "host_intr4", "host_intr5",
0128 "host_intr6", "host_intr7";
0129 interrupt-controller;
0130 #interrupt-cells = <3>;
0131 };
0132 };
0133
0134 - |
0135
0136 /* AM4376 PRU-ICSS */
0137 #include <dt-bindings/interrupt-controller/arm-gic.h>
0138 pruss@0 {
0139 compatible = "ti,am4376-pruss1";
0140 reg = <0x0 0x40000>;
0141 #address-cells = <1>;
0142 #size-cells = <1>;
0143 ranges;
0144
0145 interrupt-controller@20000 {
0146 compatible = "ti,pruss-intc";
0147 reg = <0x20000 0x2000>;
0148 interrupt-controller;
0149 #interrupt-cells = <3>;
0150 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0157 interrupt-names = "host_intr0", "host_intr1",
0158 "host_intr2", "host_intr3",
0159 "host_intr4",
0160 "host_intr6", "host_intr7";
0161 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
0162 };
0163 };
