0001 Keystone 2 IRQ controller IP
0002
0003 On Keystone SOCs, DSP cores can send interrupts to ARM
0004 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
0005 The IRQ handler running on HOST OS can identify DSP signal source by
0006 analyzing SRCCx bits in IPCARx registers. This is one of the component
0007 used by the IPC mechanism used on Keystone SOCs.
0008
0009 Required Properties:
0010 - compatible: should be "ti,keystone-irq"
0011 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
0012 access device control registers and the offset inside
0013 device control registers range.
0014 - interrupt-controller : Identifies the node as an interrupt controller
0015 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
0016 source should be 1.
0017 - interrupts: interrupt reference to primary interrupt controller
0018
0019 Please refer to interrupts.txt in this directory for details of the common
0020 Interrupt Controllers bindings used by client devices.
0021
0022 Example:
0023 kirq0: keystone_irq0@26202a0 {
0024 compatible = "ti,keystone-irq";
0025 ti,syscon-dev = <&devctrl 0x2a0>;
0026 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
0027 interrupt-controller;
0028 #interrupt-cells = <1>;
0029 };
0030
0031 dsp0: dsp0 {
0032 compatible = "linux,rproc-user";
0033 ...
0034 interrupt-parent = <&kirq0>;
0035 interrupts = <10 2>;
0036 };
