0001 * SPEAr Shared IRQ layer (shirq)
0002
0003 SPEAr3xx architecture includes shared/multiplexed irqs for certain set
0004 of devices. The multiplexor provides a single interrupt to parent
0005 interrupt controller (VIC) on behalf of a group of devices.
0006
0007 There can be multiple groups available on SPEAr3xx variants but not
0008 exceeding 4. The number of devices in a group can differ, further they
0009 may share same set of status/mask registers spanning across different
0010 bit masks. Also in some cases the group may not have enable or other
0011 registers. This makes software little complex.
0012
0013 A single node in the device tree is used to describe the shared
0014 interrupt multiplexor (one node for all groups). A group in the
0015 interrupt controller shares config/control registers with other groups.
0016 For example, a 32-bit interrupt enable/disable config register can
0017 accommodate up to 4 interrupt groups.
0018
0019 Required properties:
0020 - compatible: should be, either of
0021 - "st,spear300-shirq"
0022 - "st,spear310-shirq"
0023 - "st,spear320-shirq"
0024 - interrupt-controller: Identifies the node as an interrupt controller.
0025 - #interrupt-cells: should be <1> which basically contains the offset
0026 (starting from 0) of interrupts for all the groups.
0027 - reg: Base address and size of shirq registers.
0028 - interrupts: The list of interrupts generated by the groups which are
0029 then connected to a parent interrupt controller. Each group is
0030 associated with one of the interrupts, hence number of interrupts (to
0031 parent) is equal to number of groups. The format of the interrupt
0032 specifier depends in the interrupt parent controller.
0033
0034 Example:
0035
0036 The following is an example from the SPEAr320 SoC dtsi file.
0037
0038 shirq: interrupt-controller@b3000000 {
0039 compatible = "st,spear320-shirq";
0040 reg = <0xb3000000 0x1000>;
0041 interrupts = <28 29 30 1>;
0042 #interrupt-cells = <1>;
0043 interrupt-controller;
0044 };
