0001 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
0002
0003 Synopsys DesignWare provides interrupt controller IP for APB known as
0004 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
0005 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
0006 controller in some SoCs, e.g. Hisilicon SD5203.
0007
0008 Required properties:
0009 - compatible: shall be "snps,dw-apb-ictl"
0010 - reg: physical base address of the controller and length of memory mapped
0011 region starting with ENABLE_LOW register
0012 - interrupt-controller: identifies the node as an interrupt controller
0013 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
0014
0015 Additional required property when it's used as secondary interrupt controller:
0016 - interrupts: interrupt reference to primary interrupt controller
0017
0018 The interrupt sources map to the corresponding bits in the interrupt
0019 registers, i.e.
0020 - 0 maps to bit 0 of low interrupts,
0021 - 1 maps to bit 1 of low interrupts,
0022 - 32 maps to bit 0 of high interrupts,
0023 - 33 maps to bit 1 of high interrupts,
0024 - (optional) fast interrupts start at 64.
0025
0026 Example:
0027 /* dw_apb_ictl is used as secondary interrupt controller */
0028 aic: interrupt-controller@3000 {
0029 compatible = "snps,dw-apb-ictl";
0030 reg = <0x3000 0xc00>;
0031 interrupt-controller;
0032 #interrupt-cells = <1>;
0033 interrupt-parent = <&gic>;
0034 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0035 };
0036
0037 /* dw_apb_ictl is used as primary interrupt controller */
0038 vic: interrupt-controller@10130000 {
0039 compatible = "snps,dw-apb-ictl";
0040 reg = <0x10130000 0x1000>;
0041 interrupt-controller;
0042 #interrupt-cells = <1>;
0043 };
