0001 * ARC-HS Interrupt Distribution Unit
0002
0003 This optional 2nd level interrupt controller can be used in SMP configurations
0004 for dynamic IRQ routing, load balancing of common/external IRQs towards core
0005 intc.
0006
0007 Properties:
0008
0009 - compatible: "snps,archs-idu-intc"
0010 - interrupt-controller: This is an interrupt controller.
0011 - #interrupt-cells: Must be <1> or <2>.
0012
0013 Value of the first cell specifies the "common" IRQ from peripheral to IDU.
0014 Number N of the particular interrupt line of IDU corresponds to the line N+24
0015 of the core interrupt controller.
0016
0017 The (optional) second cell specifies any of the following flags:
0018 - bits[3:0] trigger type and level flags
0019 1 = low-to-high edge triggered
0020 2 = NOT SUPPORTED (high-to-low edge triggered)
0021 4 = active high level-sensitive <<< DEFAULT
0022 8 = NOT SUPPORTED (active low level-sensitive)
0023 When no second cell is specified, the interrupt is assumed to be level
0024 sensitive.
0025
0026 The interrupt controller is accessed via the special ARC AUX register
0027 interface, hence "reg" property is not specified.
0028
0029 Example:
0030 core_intc: core-interrupt-controller {
0031 compatible = "snps,archs-intc";
0032 interrupt-controller;
0033 #interrupt-cells = <1>;
0034 };
0035
0036 idu_intc: idu-interrupt-controller {
0037 compatible = "snps,archs-idu-intc";
0038 interrupt-controller;
0039 interrupt-parent = <&core_intc>;
0040 #interrupt-cells = <1>;
0041 };
0042
0043 some_device: serial@c0fc1000 {
0044 interrupt-parent = <&idu_intc>;
0045 interrupts = <0>; /* upstream idu IRQ #24 */
0046 };
