0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 # Copyright (C) 2020 SiFive, Inc.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: SiFive Platform-Level Interrupt Controller (PLIC)
0009
0010 description:
0011 SiFive SoCs and other RISC-V SoCs include an implementation of the
0012 Platform-Level Interrupt Controller (PLIC) high-level specification in
0013 the RISC-V Privileged Architecture specification. The PLIC connects all
0014 external interrupts in the system to all hart contexts in the system, via
0015 the external interrupt source in each hart.
0016
0017 A hart context is a privilege mode in a hardware execution thread. For example,
0018 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
0019 privilege modes per hart; machine mode and supervisor mode.
0020
0021 Each interrupt can be enabled on per-context basis. Any context can claim
0022 a pending enabled interrupt and then release it once it has been handled.
0023
0024 Each interrupt has a configurable priority. Higher priority interrupts are
0025 serviced first. Each context can specify a priority threshold. Interrupts
0026 with priority below this threshold will not cause the PLIC to raise its
0027 interrupt line leading to the context.
0028
0029 The PLIC supports both edge-triggered and level-triggered interrupts. For
0030 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
0031 seen while an interrupt handler is active; the PLIC may either queue them or
0032 ignore them. In the first case, handlers are oblivious to the trigger type, so
0033 it is not included in the interrupt specifier. In the second case, software
0034 needs to know the trigger type, so it can reorder the interrupt flow to avoid
0035 missing interrupts. This special handling is needed by at least the Renesas
0036 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
0037
0038 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
0039 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
0040 contains a specific memory layout, which is documented in chapter 8 of the
0041 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
0042
0043 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
0044 T-HEAD PLIC implementation requires setting a delegation bit to allow access
0045 from S-mode. So add thead,c900-plic to distinguish them.
0046
0047 maintainers:
0048 - Sagar Kadam <sagar.kadam@sifive.com>
0049 - Paul Walmsley <paul.walmsley@sifive.com>
0050 - Palmer Dabbelt <palmer@dabbelt.com>
0051
0052 properties:
0053 compatible:
0054 oneOf:
0055 - items:
0056 - enum:
0057 - renesas,r9a07g043-plic
0058 - const: andestech,nceplic100
0059 - items:
0060 - enum:
0061 - sifive,fu540-c000-plic
0062 - starfive,jh7100-plic
0063 - canaan,k210-plic
0064 - const: sifive,plic-1.0.0
0065 - items:
0066 - enum:
0067 - allwinner,sun20i-d1-plic
0068 - const: thead,c900-plic
0069
0070 reg:
0071 maxItems: 1
0072
0073 '#address-cells':
0074 const: 0
0075
0076 '#interrupt-cells': true
0077
0078 interrupt-controller: true
0079
0080 interrupts-extended:
0081 minItems: 1
0082 maxItems: 15872
0083 description:
0084 Specifies which contexts are connected to the PLIC, with "-1" specifying
0085 that a context is not present. Each node pointed to should be a
0086 riscv,cpu-intc node, which has a riscv node as parent.
0087
0088 riscv,ndev:
0089 $ref: "/schemas/types.yaml#/definitions/uint32"
0090 description:
0091 Specifies how many external interrupts are supported by this controller.
0092
0093 clocks: true
0094
0095 power-domains: true
0096
0097 resets: true
0098
0099 required:
0100 - compatible
0101 - '#address-cells'
0102 - '#interrupt-cells'
0103 - interrupt-controller
0104 - reg
0105 - interrupts-extended
0106 - riscv,ndev
0107
0108 allOf:
0109 - if:
0110 properties:
0111 compatible:
0112 contains:
0113 enum:
0114 - andestech,nceplic100
0115 - thead,c900-plic
0116
0117 then:
0118 properties:
0119 '#interrupt-cells':
0120 const: 2
0121
0122 else:
0123 properties:
0124 '#interrupt-cells':
0125 const: 1
0126
0127 - if:
0128 properties:
0129 compatible:
0130 contains:
0131 const: renesas,r9a07g043-plic
0132
0133 then:
0134 properties:
0135 clocks:
0136 maxItems: 1
0137
0138 power-domains:
0139 maxItems: 1
0140
0141 resets:
0142 maxItems: 1
0143
0144 required:
0145 - clocks
0146 - power-domains
0147 - resets
0148
0149 additionalProperties: false
0150
0151 examples:
0152 - |
0153 plic: interrupt-controller@c000000 {
0154 #address-cells = <0>;
0155 #interrupt-cells = <1>;
0156 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
0157 interrupt-controller;
0158 interrupts-extended = <&cpu0_intc 11>,
0159 <&cpu1_intc 11>, <&cpu1_intc 9>,
0160 <&cpu2_intc 11>, <&cpu2_intc 9>,
0161 <&cpu3_intc 11>, <&cpu3_intc 9>,
0162 <&cpu4_intc 11>, <&cpu4_intc 9>;
0163 reg = <0xc000000 0x4000000>;
0164 riscv,ndev = <10>;
0165 };
