0001 RISC-V Hart-Level Interrupt Controller (HLIC)
0002 ---------------------------------------------
0003
0004 RISC-V cores include Control Status Registers (CSRs) which are local to each
0005 CPU core (HART in RISC-V terminology) and can be read or written by software.
0006 Some of these CSRs are used to control local interrupts connected to the core.
0007 Every interrupt is ultimately routed through a hart's HLIC before it
0008 interrupts that hart.
0009
0010 The RISC-V supervisor ISA manual specifies three interrupt sources that are
0011 attached to every HLIC: software interrupts, the timer interrupt, and external
0012 interrupts. Software interrupts are used to send IPIs between cores. The
0013 timer interrupt comes from an architecturally mandated real-time timer that is
0014 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
0015 interrupts connect all other device interrupts to the HLIC, which are routed
0016 via the platform-level interrupt controller (PLIC).
0017
0018 All RISC-V systems that conform to the supervisor ISA specification are
0019 required to have a HLIC with these three interrupt sources present. Since the
0020 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
0021 entry, though external interrupt controllers (like the PLIC, for example) will
0022 need to define how their interrupts map to the relevant HLICs. This means
0023 a PLIC interrupt property will typically list the HLICs for all present HARTs
0024 in the system.
0025
0026 Required properties:
0027 - compatible : "riscv,cpu-intc"
0028 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
0029 RISC-V supervisor ISA manual, with only the following three interrupts being
0030 defined for supervisor mode:
0031 - Source 1 is the supervisor software interrupt, which can be sent by an SBI
0032 call and is reserved for use by software.
0033 - Source 5 is the supervisor timer interrupt, which can be configured by
0034 SBI calls and implements a one-shot timer.
0035 - Source 9 is the supervisor external interrupt, which chains to all other
0036 device interrupts.
0037 - interrupt-controller : Identifies the node as an interrupt controller
0038
0039 Furthermore, this interrupt-controller MUST be embedded inside the cpu
0040 definition of the hart whose CSRs control these local interrupts.
0041
0042 An example device tree entry for a HLIC is show below.
0043
0044 cpu1: cpu@1 {
0045 compatible = "riscv";
0046 ...
0047 cpu1-intc: interrupt-controller {
0048 #interrupt-cells = <1>;
0049 compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
0050 interrupt-controller;
0051 };
0052 };
