0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
0008
0009 maintainers:
0010 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
0011 - Geert Uytterhoeven <geert+renesas@glider.be>
0012
0013 description: |
0014 IA55 performs various interrupt controls including synchronization for the external
0015 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
0016 interrupts output by each IP. And it notifies the interrupt to the GIC
0017 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
0018 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
0019 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
0020 stand-up edge detection interrupts)
0021
0022 allOf:
0023 - $ref: /schemas/interrupt-controller.yaml#
0024
0025 properties:
0026 compatible:
0027 items:
0028 - enum:
0029 - renesas,r9a07g044-irqc # RZ/G2{L,LC}
0030 - renesas,r9a07g054-irqc # RZ/V2L
0031 - const: renesas,rzg2l-irqc
0032
0033 '#interrupt-cells':
0034 description: The first cell should contain external interrupt number (IRQ0-7) and the
0035 second cell is used to specify the flag.
0036 const: 2
0037
0038 '#address-cells':
0039 const: 0
0040
0041 interrupt-controller: true
0042
0043 reg:
0044 maxItems: 1
0045
0046 interrupts:
0047 maxItems: 41
0048
0049 clocks:
0050 maxItems: 2
0051
0052 clock-names:
0053 items:
0054 - const: clk
0055 - const: pclk
0056
0057 power-domains:
0058 maxItems: 1
0059
0060 resets:
0061 maxItems: 1
0062
0063 required:
0064 - compatible
0065 - '#interrupt-cells'
0066 - '#address-cells'
0067 - interrupt-controller
0068 - reg
0069 - interrupts
0070 - clocks
0071 - clock-names
0072 - power-domains
0073 - resets
0074
0075 unevaluatedProperties: false
0076
0077 examples:
0078 - |
0079 #include <dt-bindings/interrupt-controller/arm-gic.h>
0080 #include <dt-bindings/clock/r9a07g044-cpg.h>
0081
0082 irqc: interrupt-controller@110a0000 {
0083 compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
0084 reg = <0x110a0000 0x10000>;
0085 #interrupt-cells = <2>;
0086 #address-cells = <0>;
0087 interrupt-controller;
0088 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0089 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0090 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0091 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0092 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0093 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0094 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0095 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0096 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0097 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
0098 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
0099 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
0100 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
0101 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
0102 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
0103 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
0108 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
0109 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
0110 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
0111 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
0112 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
0113 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
0114 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
0115 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
0116 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
0117 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
0118 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
0119 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
0120 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
0121 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
0122 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
0123 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
0124 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
0125 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
0126 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
0127 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
0128 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
0129 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
0130 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
0131 clock-names = "clk", "pclk";
0132 power-domains = <&cpg>;
0133 resets = <&cpg R9A07G044_IA55_RESETN>;
0134 };
