0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas RZ/A1 Interrupt Controller
0008
0009 maintainers:
0010 - Chris Brandt <chris.brandt@renesas.com>
0011 - Geert Uytterhoeven <geert+renesas@glider.be>
0012
0013 description: |
0014 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
0015 RZ/A2 SoCs:
0016 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
0017 - NMI edge select.
0018
0019 allOf:
0020 - $ref: /schemas/interrupt-controller.yaml#
0021
0022 properties:
0023 compatible:
0024 items:
0025 - enum:
0026 - renesas,r7s72100-irqc # RZ/A1H
0027 - renesas,r7s9210-irqc # RZ/A2M
0028 - const: renesas,rza1-irqc
0029
0030 '#interrupt-cells':
0031 const: 2
0032
0033 '#address-cells':
0034 const: 0
0035
0036 interrupt-controller: true
0037
0038 reg:
0039 maxItems: 1
0040
0041 interrupt-map:
0042 maxItems: 8
0043 description: Specifies the mapping from external interrupts to GIC interrupts.
0044
0045 interrupt-map-mask:
0046 items:
0047 - const: 7
0048 - const: 0
0049
0050 required:
0051 - compatible
0052 - '#interrupt-cells'
0053 - '#address-cells'
0054 - interrupt-controller
0055 - reg
0056 - interrupt-map
0057 - interrupt-map-mask
0058
0059 additionalProperties: false
0060
0061 examples:
0062 - |
0063 #include <dt-bindings/interrupt-controller/arm-gic.h>
0064 irqc: interrupt-controller@fcfef800 {
0065 compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
0066 #interrupt-cells = <2>;
0067 #address-cells = <0>;
0068 interrupt-controller;
0069 reg = <0xfcfef800 0x6>;
0070 interrupt-map =
0071 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0072 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0073 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0074 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0075 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0076 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0077 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0078 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0079 interrupt-map-mask = <7 0>;
0080 };
