0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller
0008
0009 maintainers:
0010 - Geert Uytterhoeven <geert+renesas@glider.be>
0011
0012 properties:
0013 compatible:
0014 items:
0015 - enum:
0016 - renesas,irqc-r8a73a4 # R-Mobile APE6
0017 - renesas,irqc-r8a7742 # RZ/G1H
0018 - renesas,irqc-r8a7743 # RZ/G1M
0019 - renesas,irqc-r8a7744 # RZ/G1N
0020 - renesas,irqc-r8a7745 # RZ/G1E
0021 - renesas,irqc-r8a77470 # RZ/G1C
0022 - renesas,irqc-r8a7790 # R-Car H2
0023 - renesas,irqc-r8a7791 # R-Car M2-W
0024 - renesas,irqc-r8a7792 # R-Car V2H
0025 - renesas,irqc-r8a7793 # R-Car M2-N
0026 - renesas,irqc-r8a7794 # R-Car E2
0027 - renesas,intc-ex-r8a774a1 # RZ/G2M
0028 - renesas,intc-ex-r8a774b1 # RZ/G2N
0029 - renesas,intc-ex-r8a774c0 # RZ/G2E
0030 - renesas,intc-ex-r8a774e1 # RZ/G2H
0031 - renesas,intc-ex-r8a7795 # R-Car H3
0032 - renesas,intc-ex-r8a7796 # R-Car M3-W
0033 - renesas,intc-ex-r8a77961 # R-Car M3-W+
0034 - renesas,intc-ex-r8a77965 # R-Car M3-N
0035 - renesas,intc-ex-r8a77970 # R-Car V3M
0036 - renesas,intc-ex-r8a77980 # R-Car V3H
0037 - renesas,intc-ex-r8a77990 # R-Car E3
0038 - renesas,intc-ex-r8a77995 # R-Car D3
0039 - renesas,intc-ex-r8a779a0 # R-Car V3U
0040 - const: renesas,irqc
0041
0042 '#interrupt-cells':
0043 # an interrupt index and flags, as defined in interrupts.txt in
0044 # this directory
0045 const: 2
0046
0047 interrupt-controller: true
0048
0049 reg:
0050 maxItems: 1
0051
0052 interrupts:
0053 minItems: 1
0054 maxItems: 32
0055
0056 clocks:
0057 maxItems: 1
0058
0059 power-domains:
0060 maxItems: 1
0061
0062 resets:
0063 maxItems: 1
0064
0065 required:
0066 - compatible
0067 - '#interrupt-cells'
0068 - interrupt-controller
0069 - reg
0070 - interrupts
0071 - clocks
0072
0073 additionalProperties: false
0074
0075 examples:
0076 - |
0077 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
0078 #include <dt-bindings/interrupt-controller/arm-gic.h>
0079 #include <dt-bindings/interrupt-controller/irq.h>
0080
0081 irqc0: interrupt-controller@e61c0000 {
0082 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
0083 #interrupt-cells = <2>;
0084 interrupt-controller;
0085 reg = <0xe61c0000 0x200>;
0086 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0087 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0088 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0089 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0090 clocks = <&cpg CPG_MOD 407>;
0091 };
