bindings/interrupt-controller/renesas%2Cintc-irqpin.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas Interrupt Controller (INTC) for external pins
0008
0009 maintainers:
0010   - Geert Uytterhoeven <geert+renesas@glider.be>
0011
0012 properties:
0013   compatible:
0014     items:
0015       - enum:
0016           - renesas,intc-irqpin-r8a7740  # R-Mobile A1
0017           - renesas,intc-irqpin-r8a7778  # R-Car M1A
0018           - renesas,intc-irqpin-r8a7779  # R-Car H1
0019           - renesas,intc-irqpin-sh73a0   # SH-Mobile AG5
0020       - const: renesas,intc-irqpin
0021
0022   reg:
0023     minItems: 5
0024     items:
0025       - description: Interrupt control register
0026       - description: Interrupt priority register
0027       - description: Interrupt source register
0028       - description: Interrupt mask register
0029       - description: Interrupt mask clear register
0030       - description: Interrupt control register for ICR0 with IRLM0 bit
0031
0032   interrupt-controller: true
0033
0034   '#interrupt-cells':
0035     const: 2
0036
0037   interrupts:
0038     minItems: 1
0039     maxItems: 8
0040
0041   sense-bitfield-width:
0042     $ref: /schemas/types.yaml#/definitions/uint32
0043     enum: [2, 4]
0044     default: 4
0045     description:
0046       Width of a single sense bitfield in the SENSE register, if different from the
0047       default.
0048
0049   control-parent:
0050     type: boolean
0051     description:
0052       Disable and enable interrupts on the parent interrupt controller, needed for some
0053       broken implementations.
0054
0055   clocks:
0056     maxItems: 1
0057
0058   power-domains:
0059     maxItems: 1
0060
0061 required:
0062   - compatible
0063   - reg
0064   - interrupt-controller
0065   - '#interrupt-cells'
0066   - interrupts
0067
0068 if:
0069   properties:
0070     compatible:
0071       contains:
0072         enum:
0073           - renesas,intc-irqpin-r8a7740
0074           - renesas,intc-irqpin-sh73a0
0075 then:
0076   required:
0077     - clocks
0078     - power-domains
0079
0080 additionalProperties: false
0081
0082 examples:
0083   - |
0084     #include <dt-bindings/clock/r8a7740-clock.h>
0085     #include <dt-bindings/interrupt-controller/arm-gic.h>
0086     #include <dt-bindings/interrupt-controller/irq.h>
0087
0088     irqpin1: interrupt-controller@e6900004 {
0089         compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
0090         reg = <0xe6900004 4>,
0091               <0xe6900014 4>,
0092               <0xe6900024 1>,
0093               <0xe6900044 1>,
0094               <0xe6900064 1>;
0095         interrupt-controller;
0096         #interrupt-cells = <2>;
0097         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0098                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0099                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0100                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0101                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0102                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0103                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0104                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0105         clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
0106         power-domains = <&pd_a4s>;
0107     };