0001 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
0002
0003 The MISC interrupt controller is a secondary controller for lower priority
0004 interrupt.
0005
0006 Required Properties:
0007 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
0008 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
0009 - reg: Base address and size of the controllers memory area
0010 - interrupts: Interrupt specifier for the controllers interrupt.
0011 - interrupt-controller : Identifies the node as an interrupt controller
0012 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
0013 source, should be 1
0014
0015 Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
0016 use ar7240 for all other SoCs.
0017
0018 Please refer to interrupts.txt in this directory for details of the common
0019 Interrupt Controllers bindings used by client devices.
0020
0021 Example:
0022
0023 interrupt-controller@18060010 {
0024 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
0025 reg = <0x18060010 0x4>;
0026
0027 interrupt-parent = <&cpuintc>;
0028 interrupts = <6>;
0029
0030 interrupt-controller;
0031 #interrupt-cells = <1>;
0032 };
0033
0034 Another example:
0035
0036 interrupt-controller@18060010 {
0037 compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
0038 reg = <0x18060010 0x4>;
0039
0040 interrupt-parent = <&cpuintc>;
0041 interrupts = <6>;
0042
0043 interrupt-controller;
0044 #interrupt-cells = <1>;
0045 };
