0001 * Open PIC Binding
0002
0003 This binding specifies what properties must be available in the device tree
0004 representation of an Open PIC compliant interrupt controller. This binding is
0005 based on the binding defined for Open PIC in [1] and is a superset of that
0006 binding.
0007
0008 Required properties:
0009
0010 NOTE: Many of these descriptions were paraphrased here from [1] to aid
0011 readability.
0012
0013 - compatible: Specifies the compatibility list for the PIC. The type
0014 shall be <string> and the value shall include "open-pic".
0015
0016 - reg: Specifies the base physical address(s) and size(s) of this
0017 PIC's addressable register space. The type shall be <prop-encoded-array>.
0018
0019 - interrupt-controller: The presence of this property identifies the node
0020 as an Open PIC. No property value shall be defined.
0021
0022 - #interrupt-cells: Specifies the number of cells needed to encode an
0023 interrupt source. The type shall be a <u32> and the value shall be 2.
0024
0025 - #address-cells: Specifies the number of cells needed to encode an
0026 address. The type shall be <u32> and the value shall be 0. As such,
0027 'interrupt-map' nodes do not have to specify a parent unit address.
0028
0029 Optional properties:
0030
0031 - pic-no-reset: The presence of this property indicates that the PIC
0032 shall not be reset during runtime initialization. No property value shall
0033 be defined. The presence of this property also mandates that any
0034 initialization related to interrupt sources shall be limited to sources
0035 explicitly referenced in the device tree.
0036
0037 * Interrupt Specifier Definition
0038
0039 Interrupt specifiers consists of 2 cells encoded as
0040 follows:
0041
0042 - <1st-cell>: The interrupt-number that identifies the interrupt source.
0043
0044 - <2nd-cell>: The level-sense information, encoded as follows:
0045 0 = low-to-high edge triggered
0046 1 = active low level-sensitive
0047 2 = active high level-sensitive
0048 3 = high-to-low edge triggered
0049
0050 * Examples
0051
0052 Example 1:
0053
0054 /*
0055 * An Open PIC interrupt controller
0056 */
0057 mpic: pic@40000 {
0058 // This is an interrupt controller node.
0059 interrupt-controller;
0060
0061 // No address cells so that 'interrupt-map' nodes which reference
0062 // this Open PIC node do not need a parent address specifier.
0063 #address-cells = <0>;
0064
0065 // Two cells to encode interrupt sources.
0066 #interrupt-cells = <2>;
0067
0068 // Offset address of 0x40000 and size of 0x40000.
0069 reg = <0x40000 0x40000>;
0070
0071 // Compatible with Open PIC.
0072 compatible = "open-pic";
0073
0074 // The PIC shall not be reset.
0075 pic-no-reset;
0076 };
0077
0078 Example 2:
0079
0080 /*
0081 * An interrupt generating device that is wired to an Open PIC.
0082 */
0083 serial0: serial@4500 {
0084 // Interrupt source '42' that is active high level-sensitive.
0085 // Note that there are only two cells as specified in the interrupt
0086 // parent's '#interrupt-cells' property.
0087 interrupts = <42 2>;
0088
0089 // The interrupt controller that this device is wired to.
0090 interrupt-parent = <&mpic>;
0091 };
0092
0093 * References
0094
0095 [1] Devicetree Specification
0096 (https://www.devicetree.org/specifications/)
0097
