0001 * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
0002
0003 Required properties:
0004 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
0005 - reg: should contain IC registers location and length.
0006 - interrupt-controller: identifies the node as an interrupt controller.
0007 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
0008 The first cell is the IRQ number, the second cell is used to specify
0009 one of the supported IRQ types:
0010 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
0011 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
0012 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
0013 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
0014 Reset value is IRQ_TYPE_LEVEL_LOW.
0015
0016 Optional properties:
0017 - interrupts: empty for MIC interrupt controller, cascaded MIC
0018 hardware interrupts for SIC1 and SIC2
0019
0020 Examples:
0021
0022 /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
0023 mic: interrupt-controller@40008000 {
0024 compatible = "nxp,lpc3220-mic";
0025 reg = <0x40008000 0x4000>;
0026 interrupt-controller;
0027 #interrupt-cells = <2>;
0028 };
0029
0030 sic1: interrupt-controller@4000c000 {
0031 compatible = "nxp,lpc3220-sic";
0032 reg = <0x4000c000 0x4000>;
0033 interrupt-controller;
0034 #interrupt-cells = <2>;
0035
0036 interrupt-parent = <&mic>;
0037 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
0038 <30 IRQ_TYPE_LEVEL_LOW>;
0039 };
0040
0041 sic2: interrupt-controller@40010000 {
0042 compatible = "nxp,lpc3220-sic";
0043 reg = <0x40010000 0x4000>;
0044 interrupt-controller;
0045 #interrupt-cells = <2>;
0046
0047 interrupt-parent = <&mic>;
0048 interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
0049 <31 IRQ_TYPE_LEVEL_LOW>;
0050 };
0051
0052 /* ADC */
0053 adc@40048000 {
0054 compatible = "nxp,lpc3220-adc";
0055 reg = <0x40048000 0x1000>;
0056 interrupt-parent = <&sic1>;
0057 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
0058 };
