0001 NVIDIA Legacy Interrupt Controller
0002
0003 All Tegra SoCs contain a legacy interrupt controller that routes
0004 interrupts to the GIC, and also serves as a wakeup source. It is also
0005 referred to as "ictlr", hence the name of the binding.
0006
0007 The HW block exposes a number of interrupt controllers, each
0008 implementing a set of 32 interrupts.
0009
0010 Required properties:
0011
0012 - compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
0013 subsequent SoCs remained backwards-compatible with Tegra30, so on
0014 Tegra generations later than Tegra30 the compatible value should
0015 include "nvidia,tegra30-ictlr".
0016 - reg : Specifies base physical address and size of the registers.
0017 Each controller must be described separately (Tegra20 has 4 of them,
0018 whereas Tegra30 and later have 5).
0019 - interrupt-controller : Identifies the node as an interrupt controller.
0020 - #interrupt-cells : Specifies the number of cells needed to encode an
0021 interrupt source. The value must be 3.
0022
0023 Notes:
0024
0025 - Because this HW ultimately routes interrupts to the GIC, the
0026 interrupt specifier must be that of the GIC.
0027 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
0028 are explicitly forbidden.
0029
0030 Example:
0031
0032 ictlr: interrupt-controller@60004000 {
0033 compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";
0034 reg = <0x60004000 64>,
0035 <0x60004100 64>,
0036 <0x60004200 64>,
0037 <0x60004300 64>;
0038 interrupt-controller;
0039 #interrupt-cells = <3>;
0040 interrupt-parent = <&intc>;
0041 };
