0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MIPS Global Interrupt Controller
0008
0009 maintainers:
0010 - Paul Burton <paulburton@kernel.org>
0011 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
0012
0013 description: |
0014 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
0015 It also supports local (per-processor) interrupts and software-generated
0016 interrupts which can be used as IPIs. The GIC also includes a free-running
0017 global timer, per-CPU count/compare timers, and a watchdog.
0018
0019 properties:
0020 compatible:
0021 const: mti,gic
0022
0023 "#interrupt-cells":
0024 const: 3
0025 description: |
0026 The 1st cell is the type of interrupt: local or shared defined in the
0027 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
0028 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
0029 the IRQ trigger modes, which are defined in the file
0030 'dt-bindings/interrupt-controller/irq.h'.
0031
0032 reg:
0033 description: |
0034 Base address and length of the GIC registers space. If not present,
0035 the base address reported by the hardware GCR_GIC_BASE will be used.
0036 maxItems: 1
0037
0038 interrupt-controller: true
0039
0040 mti,reserved-cpu-vectors:
0041 description: |
0042 Specifies the list of CPU interrupt vectors to which the GIC may not
0043 route interrupts. This property is ignored if the CPU is started in EIC
0044 mode.
0045 $ref: /schemas/types.yaml#/definitions/uint32-array
0046 minItems: 1
0047 maxItems: 6
0048 uniqueItems: true
0049 items:
0050 minimum: 2
0051 maximum: 7
0052
0053 mti,reserved-ipi-vectors:
0054 description: |
0055 Specifies the range of GIC interrupts that are reserved for IPIs.
0056 It accepts two values: the 1st is the starting interrupt and the 2nd is
0057 the size of the reserved range. If not specified, the driver will
0058 allocate the last (2 * number of VPEs in the system).
0059 $ref: /schemas/types.yaml#/definitions/uint32-array
0060 items:
0061 - minimum: 0
0062 maximum: 254
0063 - minimum: 2
0064 maximum: 254
0065
0066 timer:
0067 type: object
0068 description: |
0069 MIPS GIC includes a free-running global timer, per-CPU count/compare
0070 timers, and a watchdog. Currently only the GIC Timer is supported.
0071 properties:
0072 compatible:
0073 const: mti,gic-timer
0074
0075 interrupts:
0076 description: |
0077 Interrupt for the GIC local timer, so normally it's suppose to be of
0078 <GIC_LOCAL X IRQ_TYPE_NONE> format.
0079 maxItems: 1
0080
0081 clocks:
0082 maxItems: 1
0083
0084 clock-frequency: true
0085
0086 required:
0087 - compatible
0088 - interrupts
0089
0090 oneOf:
0091 - required:
0092 - clocks
0093 - required:
0094 - clock-frequency
0095
0096 additionalProperties: false
0097
0098 additionalProperties: false
0099
0100 required:
0101 - compatible
0102 - "#interrupt-cells"
0103 - interrupt-controller
0104
0105 examples:
0106 - |
0107 #include <dt-bindings/interrupt-controller/mips-gic.h>
0108 #include <dt-bindings/interrupt-controller/irq.h>
0109
0110 interrupt-controller@1bdc0000 {
0111 compatible = "mti,gic";
0112 reg = <0x1bdc0000 0x20000>;
0113 interrupt-controller;
0114 #interrupt-cells = <3>;
0115 mti,reserved-cpu-vectors = <7>;
0116 mti,reserved-ipi-vectors = <40 8>;
0117
0118 timer {
0119 compatible = "mti,gic-timer";
0120 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
0121 clock-frequency = <50000000>;
0122 };
0123 };
0124 - |
0125 #include <dt-bindings/interrupt-controller/mips-gic.h>
0126 #include <dt-bindings/interrupt-controller/irq.h>
0127
0128 interrupt-controller@1bdc0000 {
0129 compatible = "mti,gic";
0130 reg = <0x1bdc0000 0x20000>;
0131 interrupt-controller;
0132 #interrupt-cells = <3>;
0133
0134 timer {
0135 compatible = "mti,gic-timer";
0136 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
0137 clocks = <&cpu_pll>;
0138 };
0139 };
0140 - |
0141 interrupt-controller {
0142 compatible = "mti,gic";
0143 interrupt-controller;
0144 #interrupt-cells = <3>;
0145 };
0146 ...
