0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MStar Interrupt Controller
0008
0009 maintainers:
0010 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
0011
0012 description: |+
0013 MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
0014 interrupt controllers that routes interrupts to the GIC.
0015
0016 The HW block exposes a number of interrupt controllers, each
0017 can support up to 64 interrupts.
0018
0019 properties:
0020 compatible:
0021 const: mstar,mst-intc
0022
0023 interrupt-controller: true
0024
0025 "#interrupt-cells":
0026 const: 3
0027 description: |
0028 Use the same format as specified by GIC in arm,gic.yaml.
0029
0030 reg:
0031 maxItems: 1
0032
0033 mstar,irqs-map-range:
0034 description: |
0035 The range <start, end> of parent interrupt controller's interrupt
0036 lines that are hardwired to mstar interrupt controller.
0037 $ref: /schemas/types.yaml#/definitions/uint32-matrix
0038 items:
0039 minItems: 2
0040 maxItems: 2
0041
0042 mstar,intc-no-eoi:
0043 description:
0044 Mark this controller has no End Of Interrupt(EOI) implementation.
0045 type: boolean
0046
0047 required:
0048 - compatible
0049 - reg
0050 - mstar,irqs-map-range
0051
0052 additionalProperties: false
0053
0054 examples:
0055 - |
0056 mst_intc0: interrupt-controller@1f2032d0 {
0057 compatible = "mstar,mst-intc";
0058 interrupt-controller;
0059 #interrupt-cells = <3>;
0060 interrupt-parent = <&gic>;
0061 reg = <0x1f2032d0 0x30>;
0062 mstar,irqs-map-range = <0 63>;
0063 };
0064 ...
