0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Microsemi Ocelot SoC ICPU Interrupt Controller
0008
0009 maintainers:
0010 - Alexandre Belloni <alexandre.belloni@bootlin.com>
0011
0012 allOf:
0013 - $ref: /schemas/interrupt-controller.yaml#
0014
0015 description: |
0016 the Microsemi Ocelot interrupt controller that is part of the
0017 ICPU. It is connected directly to the MIPS core interrupt
0018 controller.
0019
0020 properties:
0021 compatible:
0022 items:
0023 - enum:
0024 - mscc,jaguar2-icpu-intr
0025 - mscc,luton-icpu-intr
0026 - mscc,ocelot-icpu-intr
0027 - mscc,serval-icpu-intr
0028
0029
0030 '#interrupt-cells':
0031 const: 1
0032
0033 '#address-cells':
0034 const: 0
0035
0036 interrupt-controller: true
0037
0038 reg:
0039 maxItems: 1
0040
0041 interrupts:
0042 maxItems: 1
0043
0044 required:
0045 - compatible
0046 - '#interrupt-cells'
0047 - '#address-cells'
0048 - interrupt-controller
0049 - reg
0050
0051 additionalProperties: false
0052
0053 examples:
0054 - |
0055 intc: interrupt-controller@70000070 {
0056 compatible = "mscc,ocelot-icpu-intr";
0057 reg = <0x70000070 0x70>;
0058 #interrupt-cells = <1>;
0059 #address-cells = <0>;
0060 interrupt-controller;
0061 interrupt-parent = <&cpuintc>;
0062 interrupts = <2>;
0063 };
0064 ...
