0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Microchip External Interrupt Controller
0008
0009 maintainers:
0010 - Claudiu Beznea <claudiu.beznea@microchip.com>
0011
0012 description:
0013 This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
0014 support for handling up to 2 external interrupt lines.
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - microchip,sama7g5-eic
0020
0021 reg:
0022 maxItems: 1
0023
0024 interrupt-controller: true
0025
0026 '#interrupt-cells':
0027 const: 2
0028 description:
0029 The first cell is the input IRQ number (between 0 and 1), the second cell
0030 is the trigger type as defined in interrupt.txt present in this directory.
0031
0032 interrupts:
0033 description: |
0034 Contains the GIC SPI IRQs mapped to the external interrupt lines. They
0035 should be specified sequentially from output 0 to output 1.
0036 minItems: 2
0037 maxItems: 2
0038
0039 clocks:
0040 maxItems: 1
0041
0042 clock-names:
0043 const: pclk
0044
0045 required:
0046 - compatible
0047 - reg
0048 - interrupt-controller
0049 - '#interrupt-cells'
0050 - interrupts
0051 - clocks
0052 - clock-names
0053
0054 additionalProperties: false
0055
0056 examples:
0057 - |
0058 #include <dt-bindings/clock/at91.h>
0059 #include <dt-bindings/interrupt-controller/arm-gic.h>
0060
0061 eic: interrupt-controller@e1628000 {
0062 compatible = "microchip,sama7g5-eic";
0063 reg = <0xe1628000 0x100>;
0064 interrupt-parent = <&gic>;
0065 interrupt-controller;
0066 #interrupt-cells = <2>;
0067 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0068 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0069 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
0070 clock-names = "pclk";
0071 };
0072
0073 ...
