0001 Marvell SEI (System Error Interrupt) Controller
0002 -----------------------------------------------
0003
0004 Marvell SEI (System Error Interrupt) controller is an interrupt
0005 aggregator. It receives interrupts from several sources and aggregates
0006 them to a single interrupt line (an SPI) on the parent interrupt
0007 controller.
0008
0009 This interrupt controller can handle up to 64 SEIs, a set comes from the
0010 AP and is wired while a second set comes from the CPs by the mean of
0011 MSIs.
0012
0013 Required properties:
0014
0015 - compatible: should be one of:
0016 * "marvell,ap806-sei"
0017 - reg: SEI registers location and length.
0018 - interrupts: identifies the parent IRQ that will be triggered.
0019 - #interrupt-cells: number of cells to define an SEI wired interrupt
0020 coming from the AP, should be 1. The cell is the IRQ
0021 number.
0022 - interrupt-controller: identifies the node as an interrupt controller
0023 for AP interrupts.
0024 - msi-controller: identifies the node as an MSI controller for the CPs
0025 interrupts.
0026
0027 Example:
0028
0029 sei: interrupt-controller@3f0200 {
0030 compatible = "marvell,ap806-sei";
0031 reg = <0x3f0200 0x40>;
0032 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0033 #interrupt-cells = <1>;
0034 interrupt-controller;
0035 msi-controller;
0036 };
