0001 Marvell Orion SoC interrupt controllers
0002
0003 * Main interrupt controller
0004
0005 Required properties:
0006 - compatible: shall be "marvell,orion-intc"
0007 - reg: base address(es) of interrupt registers starting with CAUSE register
0008 - interrupt-controller: identifies the node as an interrupt controller
0009 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
0010
0011 The interrupt sources map to the corresponding bits in the interrupt
0012 registers, i.e.
0013 - 0 maps to bit 0 of first base address,
0014 - 1 maps to bit 1 of first base address,
0015 - 32 maps to bit 0 of second base address, and so on.
0016
0017 Example:
0018 intc: interrupt-controller {
0019 compatible = "marvell,orion-intc";
0020 interrupt-controller;
0021 #interrupt-cells = <1>;
0022 /* Dove has 64 first level interrupts */
0023 reg = <0x20200 0x10>, <0x20210 0x10>;
0024 };
0025
0026 * Bridge interrupt controller
0027
0028 Required properties:
0029 - compatible: shall be "marvell,orion-bridge-intc"
0030 - reg: base address of bridge interrupt registers starting with CAUSE register
0031 - interrupts: bridge interrupt of the main interrupt controller
0032 - interrupt-controller: identifies the node as an interrupt controller
0033 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
0034
0035 Optional properties:
0036 - marvell,#interrupts: number of interrupts provided by bridge interrupt
0037 controller, defaults to 32 if not set
0038
0039 Example:
0040 bridge_intc: interrupt-controller {
0041 compatible = "marvell,orion-bridge-intc";
0042 interrupt-controller;
0043 #interrupt-cells = <1>;
0044 reg = <0x20110 0x8>;
0045 interrupts = <0>;
0046 /* Dove bridge provides 5 interrupts */
0047 marvell,#interrupts = <5>;
0048 };
